JPS6169095A - Graphic processing method and apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a graphic processing method and device for creating graphic display data, and in particular to a graphic processing method and device for creating graphic display data, and particularly to a method for quickly calculating display memory addresses from logical coordinate values. This invention relates to a graphic processing method and device.

[Background of the invention]

FIG. 2 shows the configuration of a conventional graphic processing device, but in this case, it is not possible to convert logical addresses to physical addresses at high speed.

That is, the conventional system includes a central processing unit 60 that processes graphic data, a main memory 15 that stores a graphic data processing program, and a display memory 13 that stores graphic data.
, readout control of display memory 13 and CRT! I
A CRT control type 14 that performs I control, an address selector 16 that selects either the address from the central processing unit 60 or the address from the CRT control device 14 and then supplies the address to the display memory 13, and the display memory 13. and the central processing unit 60, a display conversion device 40 that converts the display graphic data read from the display memory 13 into a video signal, and a display device 50 that displays the graphic data. It is made up of.

Note that numerals 18 and 19 in FIG. 2 indicate an address bus and a data bus, respectively.

7 CRT screen 0″′″″″″2″′
To display the 0"55 type 2, the display is performed by sequentially reading out the graphic data stored in the read/write display memory, but the capacity of the display memory is increasing as the price of memory decreases. Therefore, in order to process large amounts of graphic data, the processing performance of graphic processing devices becomes an issue.

Now, let's consider a case where a straight line is drawn in an X-Y coordinate space with an arbitrary point as the origin, and two arbitrary points P,
Assuming that (X,, Y,), P, (X,, Y,) are connected by a straight line, calculate the slope of the straight line from the coordinate values of those two points, and calculate the coordinate values of the points on the straight line. By calculating, graphic data is created for each point and then written. Such processing is performed sequentially for all points on the straight line, but the calculated coordinate values are completely different information from the memory address of the display memory where the graphic data is written, so the calculated coordinate values are The coordinate values (logical addresses) must be converted to display memory addresses (physical addresses).

By the way, since 1g of 1 display memory contains single or multiple pixel data, the calculated logical address is divided into two parts, such as the memory address of the display memory and the bit address indicating the pixel position. It will be translated into a physical address.

To convert from a logical address to a physical address, it is necessary to know the physical address corresponding to the origin and the horizontal size of the screen memory. In other words, since the logical address is information indicating the relative position from the origin, the logical address is (X, Y
), in the vertical direction (Y direction), the horizontal size of the screen memory is multiplied by 7, and in the horizontal direction (X direction), the value of X is the number of pixels included in one word. The target memory address can be calculated by adding or subtracting the value divided by the physical address corresponding to the origin. Furthermore, the value of X is 1
By using the remainder after dividing by the number of pixels included in a word as a bit address, a physical address for processing one graphic data can be obtained.

However, up until now, calculation of logical addresses and conversion to physical addresses have been completely performed by software program processing, so when using a general-purpose microprocessor, it is necessary to store one pixel data in the display memory. The actual situation is that it takes several microseconds to several tens of microseconds to process, making it impossible to speed up the processing.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a graphic processing method and apparatus that can quickly obtain a physical address corresponding to a logical address.

[Summary of the invention]

For this purpose, the present invention calculates a logical address using hardware, and at the same time calculates a physical address using hardware in accordance with the logical address calculation, thereby performing graphical processing. It is equipped with means for calculating and means for calculating a physical address according to logical address calculation.

[Embodiments of the invention]

Hereinafter, preferred embodiments of the present invention will be described based on the drawings, but before that, the matters on which the present invention is based will be described.

The matters forming the basis of the present invention will be explained below.

The present invention is as follows.

First of all, one pixel is (a) expressed with 1 bit, (b) expressed with 2 bits, (c) expressed with 4 bits, (d) expressed with 8 bits. (s)
It is now possible to select from five pixel modes, such as 16-bit expression (see #9@).

Second, we adopted a pixel address, and this pixel address consists of one address information MAD that specifies the address of the display memory, and one that specifies the position within one word specified by that address. and address information WAD (see FIG. 10).

Third, one word of display data at the memory address specified by the address information in the pixel address is read from the display memory, and then one word of display data specified by the address information in the pixel address is read out from the display memory. $tyRPf
Jf-51, huh? 1, oh. 6□.

Moreover, it is written again into the corresponding address section of the display memory, and multiple bit data for one pixel can be processed simultaneously.

Next, examples of the present invention will be described.

Further, in the following description, the same reference numerals indicate the same objects.

FIG. 3 is a block diagram showing an example of a device to which a graphic processing device according to the present invention is applied.

In FIG. 3, the graphic processing device is composed of an arithmetic device 30 that controls writing, rewriting, and reading of display data in the display memory 13, and a control device 20 that controls the arithmetic device 30 in a fixed order. ing. Further, display data read out from the display memory 13 by the graphic processing device is converted into a video signal by the display conversion device 4o and displayed on the display device 50.

The arithmetic unit 30 sequentially calculates a pixel address consisting of an address in the display memory 13 and information specifying a pixel position in one word of display data in the display memory 13, and displays the pixel address at the calculated pixel address. One word of display data in the display memory 13 is read from the address information of the display memory 13, and the thus read display data is decoded and formed based on the pixel position designation information at the pixel address. Using information specifying a plurality of bit positions corresponding to a designated pixel position, drawing logic is calculated only for the bits of a predetermined pixel of the display data, and the result of such logical operation is written back to the display memory 13. be.

Note that 60 is an external computer, and the graphic processing device operates according to control data from this external computer 60.

FIG. 4 is a block diagram showing an embodiment of a graphic processing apparatus according to the present invention. - In the figure, the control device 20 includes a microprogram memory 100 and a microprogram address register 1.
10, a return address register 120, a microinstruction register 130, a microinstruction decoder 200, a flag register 210, a pattern memory 220,
The instruction control register 230 is configured to include an instruction control register 230.

Further, the calculation unit [30 is a calculation control device 300.

First-In, First-Out
(FIFO)) memory 400.

Each component is used in normal digital control and does not require any special explanation. However, according to this embodiment, the arithmetic control device 300 includes a logical address calculation section (A unit) 310 and a physical address calculation section (B unit).
320, and a color data calculation section (C unit) 330.

The A unit 310 mainly calculates where the drawing point is located on the screen according to the drawing algorithm, the B unit 320 calculates the necessary address of the display memory, and the C unit 330 calculates the color data to be written to the display memory. It is calculated.

FIG. 5 shows an example of the configuration of a display device that displays one pixel with 4 bits, and shows a configuration in which display data specified by the graphic processing device of FIG. 4 is displayed on the display device 50. has been done.

In FIG. 5, display data DT is read out from the display memory 13 based on the address register from the graphic processing device (FIG. 4). .

D4. D, , Di2 are supplied to a 4-bit parallel-to-serial converter 410 within the display converter 40. This converter 41
A video signal VDO is obtained from 0. Similarly, D, D, of the display data DT.

D, ,D, , are supplied to a parallel-to-serial converter 420 in the display conversion device 40, and the video signal VDI is supplied from this converter 420.
(7)02,D out of 1 display data DT that can be obtained.
-= Di-= ]: Display conversion device for h+! 40, and a video signal VD2 is obtained from this converter 430. In addition, display data DT
Uchinori, , D, , D1□, Dl.

is supplied to a parallel-to-serial converter 440 in the display conversion device 40, and a video signal VD3 is obtained from this converter 440.

The video signals VDO to VD3 are sent to a video interface circuit 450 constituting the display conversion device 40, and are displayed on the display device 50 after undergoing processing such as color conversion and DA conversion.

Next, the specific configuration of each unit of the arithmetic and control device 300 will be explained with reference to FIGS. 6 to 8.

Logical address calculation section 3, which is unit A in FIG.
10 is as shown in FIG.
FBIJF) 3LQL, general-purpose register 3102,
Area management registers 3103 and 3105, area judgment comparator 3104, end point register 3106, end judgment comparator 3107, source latches 3108 and 3109
, an arithmetic logic unit (ALU) 3110 , a destination latch (DLA) 3111 , and a bus switch 3112 .

It includes read buses (UBA, UBB) 3113 and 3114 and a write bus (WBA) 3115.

In FIG. 7, the physical address calculation section 320, which is the B unit, has a destination latch (DLB) 32.
01 and an arithmetic unit (AU) 3202.

Source latches 3203 and 3204, offset register 3205, screen width register 3206, command register 3207, general purpose register 3208, read bus (UBB) 3209, and write bus (W
BB) 3210. Note that the general-purpose register 3208 is a current address register (DPH) for a 1-pixel unit command.

DPL) and word unit command address register (Rw
PH, RWPL) and one working register (T2H.

T, L).

Furthermore, in FIG. 8, the color data calculation section 330, which is the C unit, has a barrel shifter 3301.

Color register 3302, mask register 3303, color comparator 3304, logical operator 3305, write data buffer 3306, pattern RAM buffer 3307, pattern counter 3308, pattern control register 3309, read data buffer 33
10, a memory address register 3311, a memory output bus 3312, and a memory input bus 3313. The mask register 3303 is a register (CM
SK) and a register (GMSK).

The operation of the embodiment configured as described above will be explained.

First, the basic operation of each element will be explained. Control data CDT such as commands and parameters sent from another device such as a central processing unit is written to the memory 400 on the one hand, and directly to the command control register 230 on the other hand.

The register 230 stores various graphic bit modes, as will be described later.

According to this embodiment, one can be selected from five pixel modes. This selection is based on usage data C.
This can be done with DT.

The memory 400 is a so-called “First-In, Fi
rst-Qut" (hereinafter also referred to as FIFO) memory, and the instructions stored in the memory 400 are read by the arithmetic control unit 300 and stored in the register within the arithmetic control device 300. Also, part of this instruction information The section CID is transferred to address register 110.

Address register 110 is microprogram memory 1
00 address is managed, and this address is updated in synchronization with the clock. Microprogram memory 10 according to the address output from address register 110.
The instruction read from the memory LOO consists of 48 bits as shown in FIG. 13, and one of the control modes #0 to #7 can be selected. It has become. The command is temporarily stored in the register 130, and a predetermined control signal CCS is generated via the decoder 200, which operates according to the mode selected by the register 230, to control each part of the arithmetic control device 300. Here, the function of each field of the microinstruction shown in FIG. 13 will be explained.

In FIG. 14, rRUJ is an instruction that specifies a register connected to the UBA bus 3113.

rRVJ is an instruction that specifies a register connected to the VBA path 3114.・RWJ is WBA bus 3115
This is an instruction that specifies the register to which the above data will be written. rFUNcA J is an instruction that specifies the operation of the arithmetic and logic unit 3110 of the A unit. rsFTJ
is a shifter (SFTA) added to the source latch 3108.
) This is an instruction that specifies the shift mode of f.

rADF-LJ is an instruction that specifies the lower 4 bits of the next address returned to the microprogram address register 110. rACJ is an instruction that controls the next address of a microinstruction. rADF-HJ is an instruction that specifies the upper six bits of the next address returned to the microprogram address register 110. Furthermore, the upper 6 bits of the address cannot be updated in each of the microinstructions #4 to #7.

rFUNCB J is an instruction that specifies the operation mode of the arithmetic operation unit 3202 of the B unit. rEcDJ is an instruction that specifies execution conditions for an operation. rBCDJ is an instruction that specifies branch conditions. rFLAGJ is an instruction that specifies reflection of a flag in the flag register 210.

"V" is an instruction specifying whether or not to test whether or not access to the display memory 13 is possible. rFIFOJ is an instruction that controls reading and writing to the FIFO 400.
rLITERAL J is an instruction that specifies 8-bit literal data. rLCJ is an instruction that specifies the literal data generation mode.

rFFJ is a set of special flip-flops for each part.

This is a command to control reset. "S" is an instruction specifying selection of a code flag. rMcJ is display memory 1
This is an instruction to control the read/write of No. 3. rDRJ is a command that controls scanning of the pattern RAM. rBc:
j is an instruction that controls the input path to the arithmetic operation unit 3202 of the B unit.

rRBJ is an instruction to select the read/write register of the B unit.

The micro-instructions include the above-mentioned instructions, by which the control device 20 controls the arithmetic device 30.

Note that the return address register 120 stores the return address of the subroutine. Flag register 210 stores various condition flags. The pattern memory 220 stores a certain pattern used for graphic processing.

Now, the operation of storing image data in memory will be explained, but before that, the bit layout of each data used in this embodiment will be explained.

First, the graphic mode will be explained.

In this embodiment, five different operating modes can be selected according to the designation of the graphic bit mode (GBM) stored in the command control register 230.

FIG. 9 shows the bit configuration of one word of the display memory in each mode.

(a) 1 bit/pixel mode (GBM=“OOO”)
This is a mode used when one pixel is expressed by one bit, such as in a black and white image, and 166 consecutive pixel data are stored in one word of the display memory.

(b) 2-bit/pixel mode (GBM=OO1) This mode expresses one pixel with 2 bits, and can be used for display of up to 4 colors or 4 gradations. therefore,
One word of the display memory 13 can store data of eight consecutive pixels.

(c) 4-bit/pixel mode (GBM=010) In this mode, one pixel is expressed with 4 bits, and data of four consecutive pixels can be stored in one word of data in the display memory.

(d) 8-bit/pixel mode (GBM=Oll) In this mode, one pixel is expressed with 8 bits, and data for two pixels can be stored in one word of the display memory.

(e) 16-bit/picture search mode (GBM=100) In this mode, one pixel is expressed with 16 bits, and one word in the display memory corresponds to one pixel data.

Next, pixel addresses will be explained.

FIG. 10 explains pixel addresses corresponding to each mode in FIG. 9. The register 3208 of the physical address calculation unit manages a bit address (physical address) BAD, which is a memory address with four lower bits added. The lower 4 bits of information WAD are used to specify the pixel position within one word, and operate according to each bit/pixel mode.

In the figure, the u-umbrella It symbol indicates bits that are unrelated to the operation.

FIG. 11 shows the "4-bit/pixel mode J" in item (0) above.
This figure shows the spatial arrangement of the display memory as an example. The memory address is assigned as a linear address as shown in the memory map of Figure (A), and this is displayed as a two-dimensional image as shown in Figure (B). The width of the screen is stored in a screen width register (MW) 3206 in FIG. 7, and this MW indicates how many bits the width of the screen is made up of. Therefore, in the case of 4 bits/pixel mode, MW/4 pixels are displayed in the horizontal direction. Furthermore, since one pixel is displayed using 4 bits, data for one word is displayed as data for four consecutive pixels in the horizontal direction, as shown in FIG. 11(C). The offset generation circuit 2001 in FIG. 7 generates an offset value of "4" and stores it in the offset register. Therefore, it can be seen that in order to move the physical address by one pixel in the horizontal direction, it is sufficient to add or subtract the offset value. Furthermore, to move by one pixel in the vertical direction, the value of the register (MW) 3206 may be added or subtracted.

An example of the bit layout of data used in this embodiment has been described above.

Next, the operation of storing image data in the display memory 13 using these data will be explained.

Control data CDT such as commands and parameters sent from an external central processing unit are written to the memory 400 on the one hand, and to the command control register 230 on the other hand.

Here, the designated graphic bit mode (GBM) stored in the instruction control register 230 is, for example, 4.
The case of bit/1 pixel mode (GBM=010) will be explained.

When the graphic bit mode (G B M ) is specified as 4 bits/pixel by the instruction control register 230, one word of data in the display memory 13 is divided into four bits as shown in FIG. It will be treated as such.

CDTs such as commands and parameters from an external central processing unit are stored one after another in the memory 400. The data stored in the memory 400 is taken into the FIFO buffer 3101 by the A unit 310. The operation of the A unit 310 will be explained below. The data taken into this FIFO buffer 3101 is exchanged with an internal bus 3113 and stored in each necessary register. This is connected to the logic operator 3110 via the bus link latch 3109.
A predetermined calculation is performed on the signal, and the result is temporarily stored in a destination latch (DLA) 3111.

This result is stored in general purpose register 3102. This general-purpose register 3102 stores the current coordinate point in the coordinate space.

The current X-Y coordinates in general register 3102 are read from one of read buses 3113.3114.

It is input to an arithmetic logic unit (A L u ) 3110 . The result calculated by this calculation unit (A L u ) 3110 is sent to the destination latch (DL
A) 3111, stored again in general purpose register 3102 via write bus 3115; These series of operations are the first
It will be executed according to the instructions of the microprogram shown in FIG.

Furthermore, the data on the write bus 3115 is input to the area management registers 3103 and 3105, and the area judgment comparator 3
104 for comparison. The comparator 3104 determines whether the data on the write bus 3115 is between the minimum value of the X-axis and the maximum value of the X-axis, or the minimum value of the Y-axis and the maximum value of the Y-axis. The determination result is sent to the flag register 210.

Further, the data on the write bus 3115 is stored in the end point register 3106, and is passed through the end point register 3106 to the end point register 3106.
07 is input. The end determination comparator 3107 compares the end points of the X and Y axes stored in this register 3106 in advance with the data on the write bus 3115, and determines whether the end points match the above data. Detection is performed. The comparison detection result is in the flag register 21.
reflected in 0.

As described above, comparators 3104 and 3107, arithmetic unit 3
The results of 110 are collected in flag register 210 and
It is input to the microinstruction decoder 200 and used to change the flow of the microprogram.

As described above, the A unit 310 operates and
It reads the x-y coordinate values given by the parameter and interprets commands such as drawing a line or writing 1 yen.

Next, the operation of the B unit 320 will be explained.

The data interpreted by A unit 310 is stored in register 320.
8 is input. The data in the register 3208 is sent to the arithmetic unit (
AU) 3202. The result calculated by this calculator 3202 is sent to the destination latch 3201.
temporarily stored in each bus 3113.3114.320.
9 and 3210. Here, bus 3210
The data is written to the register 3208 via the . The register 3208 has one word consisting of two 16-bit words, and stores a physical address in one word of 32 bits in total. The register 3208 has three types of 32-bit registers and can store three types of data. That is, the register DP of the register 3208 stores the physical address of the actual drawing point corresponding to the current drawing point xY. Therefore, when the xY coordinates of the register 3102 of the A unit 310 move, the physical address of the register DP moves correspondingly.

To change the physical address, in the X-axis direction, add or subtract a variably settable predetermined value (offset value x value to the point you want to move) to the original physical address, and in the Y411 direction, add or subtract a predetermined value to the original physical address. It is sufficient to perform addition and subtraction; that is, a constant degree for moving the pixel address by one pixel in the horizontal direction is set in the offset register 3205 based on information specified by the offset generation circuit 2001. By operating this constant and data in the computing unit 3202, the physical address after horizontal movement is calculated. For example, when the pixel mode is "1 bit/pixel mode", the constant may be 1, and moving one pixel results in a shift of only one bit. When this is the "4 bit/pixel mode", the constant is 4, and moving one pixel results in a shift of 4 bits.

Further, in order to move vertically by one pixel, the constant set in the screen width register 3206 is used for calculation, thereby making it possible to move by one pixel.

As described above, the B unit 320 operates to obtain an actual physical address corresponding to the x-y coordinates determined by the A unit 310.

Next, the operation of the C unit 330 will be explained.

The C unit 330 is connected to the display memory 13 shown in FIG. 11 through an output bus 3312 and an input bus 3313. To the output bus 3312, the C unit 330 first outputs address information AD, and then outputs data DT.

First, address information AD passes through B unit 320,
and is written to the memory address register 3311 via the UBB bus 3209;
1 (MARL) and (MARI()).

When the memory address stored in this register 3311 is sent to the display memory 13 via the output bus 3312, the display data DT of one word specified in the memory 13 is sent from the display memory 13 via the input bus 3313. is read out. The read display data DT is stored in the read data buffer 3310.

Here, if the display data DT draws a figure, the arithmetic unit 33
05 is input.

Next, microphone information (information specifying which bit of one word is to be masked) from the mask register 3303 is input to the arithmetic unit 3305. In addition, mask information is available from WBB
Register written directly from bus 3201 (CMSK)
, or from a register (GMSK) that stores data generated by address decoder 2002 within one word.

In addition, color information is selected in the color register 3302 and calculation M! ! Give to 3305. Then, the arithmetic unit 3305 performs a logical operation based on the data DT, mask information, and color information, and writes the result of the operation to the register 3306.
Output to. In addition, 1 color information and pattern information.

Pattern counter 3308 and drawing pattern register 3
The data is stored from the pattern RAM 220 into the pattern RAM buffer 3307 by being specified by the address signal formed in step 309 . Color register 3
300 or directly calculate f
input to the device 3305.

In this manner, the C unit 330 operates to perform conversion processing on color information.

Next, the drawing calculation method will be explained. Figure 12 shows 4 bits/
This is a diagram schematically showing the flow of drawing calculations for one pixel in pixel mode.

Drawing pattern register 33o9 and pattern register 3
The pattern RAM 22 is stored by the address specified in 308.
The data read from 0 is stored in the pattern RAM buffer 33.
07 and selects the color register 3302. In addition, the data (C, , C,
,C,,C,) are stored in the read data buffer 3310. Color data and data are each 4-bit color information or gradation information. One bit of pattern information is read from the pattern memory 220, and color register O or color register 1 is selected depending on whether the data is "0" or '1n, and is supplied to the logical operator 3305. Memory address register 331
The lower 4 bits of the physical address information stored in 1 are "10 digits" in the figure, and this information is obtained by the 1 modest address decoder 2002 and the master register 3303 generates mask information GMSK. On the other hand, the upper field of the memory address register 3311 excluding the lower 4 bits is output as a display memory address and is stored in the display memory 13.
One word is read out. The logical operator 3305 performs a logical operation only on the portion designated by the GMSK "1" bit of the mask register 3303 to obtain write data cy, which is stored in the write buffer 3306. Here, the types of logical operations performed by the arithmetic unit 3305 include replacement with color register values, logical operations (AND, OR, FOR), and conditional drawing (drawing only when the read color satisfies a predetermined condition). be. When the bit/pixel mode is another mode, similar calculations are performed except that the generated GMSK information is different. Then, the address information AD and the data DT are again sent in this order from the address register 3311 and the register 3306 to the output path 3312 and written to a predetermined address in the display memory 13.

As described above, according to the present embodiment, data for one pixel can be updated at a time by one read/update/write process, thereby enabling rendering with high processing efficiency. Furthermore, even in cases other than the 16-bit/pixel mode, since the data of multiple pixels is packed into a 16-bit length and processed, memory usage efficiency is high and data transfer efficiency between other devices and the display memory is also high. Furthermore, in this embodiment, operation modes for five different bit lengths per pixel are provided, resulting in a highly versatile configuration.

Next, graphical processing in which a physical address corresponding to a logical address can be obtained at high speed according to the present invention will be described. That is, A-UN I T (310) and B-U in FIG.
A case will be described in which address translation is performed at high speed using NIT (320).

FIG. 1 shows what is related to address translation and what is particularly added based on the configuration shown in FIGS. 6 and 7. Components that are the same as those in FIGS. 6 and 7 are designated by the same reference numerals.

The selector 3500 is controlled by the CC8, selects either data from the memory width register 3206 (MW) or data from the offset data register 3205 (○FS), and supplies it to the arithmetic unit 3202 (AU).

A computing unit 3202 computes a physical address corresponding to a logical address. Next, the physical address space, the corresponding logical address space, and the display screen corresponding to these will be explained. FIG. 14 shows a physical address space in a mode in which one pixel is represented by 4 bits, a corresponding logical address space, and four corresponding display screens. The relationship between the physical address, the display memory in the logical address space, and the display screen is as shown in the figure. In the physical address space, one 16-bit word contains 4 pixels of pixel data, each pixel represented by 4 bits, but in this case, 1 pixel is divided into memory planes for each color in the memory in the logical address space. Each], bits are assigned to
The king pixel displayed in is output on the screen. The 4f pixel data within one word becomes horizontally continuous pixel data in the memory in the logical address space and on the display screen.

FIG. 15 shows the relationship between the physical address, logical address, memory width MW, and pointer address PA shown in FIG. 14. First, FIG. 15(a) shows a memory address MA and a bit address BA in the physical address space.
Furthermore, the relationship between it and the display screen is shown. When the memory address of one word including one pixel vertically adjacent to one pixel in one word pointed to by memory address MA1 is MA2, the memory width MW becomes as shown in FIG. 15(C). Any point (, x, y
) whose corresponding physical address is the memory address MA, and whose bit address is indicated by BA, the pointer address is expressed as shown in FIG. 15(b).6By the way, as shown in FIG. In the example, 1
It has a function that can efficiently process even when pixel data is expressed in multiple bits (multiple colors or multiple gradations), and five different operation modes can be selected according to the bit mode set for the bit mode register 230. It is possible.

FIG. 16 shows the correspondence between the bit modes shown in FIG. 15 and the corresponding bit addresses indicating pixel positions within one word. According to this, the bit address is matched with the data start bit number of the pixel data. For example, in the case of the 4-bit/pixel mode, when bits 4 to 7 of the pixel data are operated on by the pixel data operation section 230, 4 is stored as the bit address of the lower 4 bits of the pointer address register 3208.

FIG. 17 shows the relationship between mask data stored in the mask register 3303 and bit addresses in the case of 4-bit/pixel mode. As mentioned above, when bits 4 to 7 of pixel data are operated, 4 is generated as the bit address, but in this case, the mask data is set to "1" only in correspondence with the bit on which pixel data operation is performed, and the pixel data is 1'0'' is set corresponding to the bit that does not require the operation. That is, 1. For example, if the bit address is 1'4'', only bits 4 to 7 are di 1 #.
The mask data marked with # is sent to the mask data generator 2002.
is generated and stored in the mask data register 3303.

FIG. 18(a) shows the basic arithmetic processing executed by the logical address arithmetic unit and the physical address arithmetic unit in the embodiment shown in FIG. 1, and FIG. 18(b) shows the bit address offset in each bit mode. To explain it in terms of the bit address offset value, which indicates the value of the bit address offset value n generated by the generator, this is for updating the bit address, and is a 4-bit/bit address offset value.
In the pixel mode, data of re 4 n and in the 1 bit/pixel mode, data of 111'' is generated by the offset generator 2001 and stored in the offset data register 3205.

Now, to explain the process shown in FIG. 18(a),
This means that the logical address at P indicating the current pixel is (x,
y), assuming that the physical address is represented by PA, point P in the horizontal or vertical direction as a logical address by ±1
This figure shows the processing in the case of moving by . First, point P to draw pixel data in the positive direction of the X axis (horizontal direction)
When adding +1 to the logical address calculation unit 310, the data (
X) is read out, and +1 is added by the arithmetic unit 3110 via the source latch 3109. The calculation result (X+1) is stored again as a new logical address into the current pointer (cpx of 3102) via the destination latch 3111.At the same time, the physical address calculation unit 320 converts the pointer from the pointer address 3208 to the current pointer (cpx of 3102). After the address is read out, it is sent to the arithmetic unit 3202 via the source latch 3204.
is given as calculation data.

On the other hand, the data from the offset data register 3205 is selectively outputted from the calculation data selector 3500 and is applied to the calculation unit 3202 as calculation data via the source latch 3203. In other words, the arithmetic unit 3202 calculates the point,
An addition is performed between *yF' and xpAhg huff "n'" 71 degrees. This addition result (PA
+n) is passed through the destination latch 3201 again as a new pointer address to the pointer address register (DPL of 3208).

DPH). After this storage, 2002 that generates mass data is a pointer address register 32.
Mask data is generated according to the lower 4 bits of data stored in 08, that is, the bit address and bit mode.The mask data is sent to the pixel data calculation unit 3305 via the mask register 3303, and is used to calculate the pixel data. It will be served.

Furthermore, when moving the point P by +1 in the positive direction of the Y direction (vertical direction), the logical address calculation unit 310 similarly performs a calculation to increment the data of the current pointer Y (CPY of 3102) by +1. . On the other hand, the physical address calculation unit 320 simultaneously operates the pointer address register 320g (D P L ).

DPH) data cannot be operated on. In the calculations in the X direction, addition and subtraction are performed with the offset value, but in the calculation in the Y direction, addition and subtraction (in this case, subtraction) are performed with the data from the memory width register 3206. The arithmetic control signal generator 200 generates addition and subtraction signals to the arithmetic unit 3202 in the physical address arithmetic unit 320 when the logical address arithmetic unit 310 performs addition and subtraction in the X direction.
When performing addition and subtraction in the Y direction with 0, the arithmetic unit 320
2, subtraction and addition signals are generated, which are determined by the address assignment of the display memory corresponding to the display screen. By performing the above-described arithmetic processing, the physical address of the point P after it has been moved is calculated.

FIG. 19 shows an example of processing when a straight line is displayed on the screen using the hardware configuration according to the embodiment of the present invention shown in FIG.

Starting point p m (x − Hy −) of straight line drawing processing
When drawing a straight line from P-(x-w y-) to the end point P-(x-w y-), first, as a first preprocessing, the physical address of the origin is transferred from the central processing unit or other control device to the pointer address register (DPL, DPH of 3208). At the same time, the current pointer X (CPX of 3102
) and the current pointer Y (cpy in 3102) are cleared to II OII under control from the control unit 200. By setting the origin in this way, the correspondence between the logical address and the physical address is established.In the second preprocessing of the 0th order, the logical address (x-yya) of the starting point P of the straight line is set as the current Pointer X CCP
Based on this, the physical address calculation unit 320 stores the logical address (xmy
y-) The corresponding physical address is now required. FIG. 3 shows the process of ending P, logical address (x, ,
y, ) is stored in the temporary register group 3102, and all preprocessing is now complete. Now, the control unit 200 receives a point P from the central processing unit or other control device.
, receives a command to draw a straight line from point P to point P, and starts this process.To execute this process, control is applied to each calculation unit 310, 320, and 330 based on the control procedure stored in advance. It is designed to be output. In the logical address calculation unit 310, intermediate information necessary for drawing processing, such as the slope of a straight line, is calculated from the logical address (Xm+3'#) of the starting point P and the ending point P.
, is calculated from the logical address (x,, y,) of , and stored in the temporary register group 3102. Based on these data, the logical address (x, , y,) of the next drawing point P is calculated.

The physical address corresponding to the logical address (X1y yt) of y, ) and ' is calculated.

While a total of two address operations, an address operation in the X direction and an address operation in the Y direction, are being executed in the logical address operation section 310 and the physical address operation section 320, these operations are performed in parallel on the corresponding pixel at the starting point P. Data is read from the display memory, and pixel data calculations at the starting point P are performed. After the calculation of this pixel data is completed, the pixel data after the calculation is written again into the display memory. That is, while two memory accesses are being executed for a certain point, in parallel, the logical address calculation unit 310 and the physical address calculation unit 320 calculate the logical address for the next drawing point and the corresponding object f. This is for calculating an address. By repeating such processing until the end P of the straight line, pixel data for straight line drawing is sequentially stored in the display memory.

Note that the pixel data read from the display memory is specially replaced with constant data and stored in the display memory again, but generally pixels existing on a drawn straight line have the same brightness or the same value. It doesn't necessarily have to be the color. Therefore, in such cases, the read pixel data is subjected to some calculations with other data, and the calculation results are stored in the display memory as new display pixel data. This is the result.

Although the present invention assumes that the logical space is two-dimensional, it is generally applicable to two-dimensional or more.

〔Effect of the invention〕

As described above, the present invention has the advantage that even when pixel data is represented by a plurality of bits, the physical address corresponding to the logical address can be obtained at high speed at the same time as calculating the logical address.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the structure of a conventionally commonly used display device, and FIG. 3 is a diagram showing a device to which the graphic processing device according to the present invention is applied. 4 is a block diagram showing an embodiment of a graphic processing device according to the present invention, FIG. 5 is a block diagram showing a display device to which the embodiment is applied, and FIGS. FIG. 9 is an explanatory diagram showing the bit layout of display data used in the embodiment;
FIG. 10 is an explanatory diagram showing the bit layout of pixel addresses used in the same embodiment, and FIG. 11 is a block diagram showing the configuration between the image memory and the display device. FIG. 12 is an explanatory diagram for explaining the drawing calculation operation of the same embodiment, FIG. 13 is an explanatory diagram showing the format of the macro instruction used in the same embodiment, and FIG. 14 is an explanatory diagram showing the format of the macro instruction used in the same embodiment. FIG. 15(a) is a diagram showing the relationship between the physical address space, the corresponding logical address space, and the display screen corresponding to these in the case where the memory address and bit address in the physical address space are Furthermore, FIGS. 15(b) and 15(c) are diagrams showing the relationship between these and the display screen, and FIG. 16 is a diagram showing the format of pointer address and memory width data, respectively. A diagram showing bit addresses as corresponding pixel positions within one word. FIG. 17 is a diagram showing the relationship between mask data and bit addresses when one pixel is represented by 4 bits.
FIG. 18(a) is a diagram for explaining the basic arithmetic processing executed in the address calculation section and physical address calculation section in FIG. 1, and FIG. 18(b) is a diagram showing the bit address offset corresponding to each bit mode. The diagram showing the values, Figure 19, is
FIG. 3 is a diagram for explaining straight line drawing processing according to the present invention. 20...Control device, 30...Arithmetic device, 300...
- Arithmetic control unit, 310... logical address calculation unit, 3
20...Physical address calculation unit, 330...Color data calculation unit. f (embedded patent attorney Katsuo Ogawa, 3rd, 5th, 8th, 9th AD, 11th (C) 12th, 185 (a,) Cb)

Claims (1)

[Claims] Every time a logical address as a coordinate point in a logical space of one or two dimensions or more is calculated by hardware as being adjacent to the logical address calculated immediately before, the and updates the physical address corresponding to the logical address calculated just before using hardware according to the adjacent direction, and then updates the pixel data corresponding to the address in the display memory to a predetermined value based on the updated physical address. A figure processing method characterized by: 2. A graphic processing device that reads pixel data stored as updatable from a display memory in a predetermined order and then displays based on the data, which uses a logical address as a coordinate point in a two-dimensional or more logical space. , a logical address calculating means that is calculated by hardware as being adjacent to the logical address calculated immediately before and temporarily stored; A figure characterized by a configuration comprising at least a physical address calculation means for updating and temporarily storing a physical address corresponding to a logical address that has been written in hardware, and a control means for controlling the means and the logical address calculation means. Processing equipment. 3. The calculation of the physical address by the physical address calculation means is controlled by at least one of means for setting and storing the number of bits of pixel data and means for setting and storing the width of the logical space. 2. Graphic processing device according to item 2.