JPS6161470A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable to rewrite a nonvolatile semiconductor memory device at higher speed by extending a conductive projection on a reverse conductive type high density impurity region to a semiconductor substrate through a tunnel insulating film along the side wall of a floating gate, thereby reducing a tunnel region. CONSTITUTION:A projection 16 is extended along a side wall through a tunnel insulating film 19 remaining on the side wall of a floating gate 13, and is contacted directly with an N<+> type layer 122. Thus, electrons are communicated through the film 19 on the side wall of the gate 13, and since the occupying area of the tunnel region depends upon the thickness of the gate 13, the tunnel region can be reduced. Accordingly, a rewriting can be performed with a low writing voltage by the electric field concentration upon reducing of the tunnel region. Since the film 19 extends perpendicularly to a P type silicon substrate 11, the occupying are of the film 9 in a memory cell becomes extremely small to be adapted for microminiaturization of the memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a non-volatile memory device having a floating gate and a 1UU control gate, and relates to a memory device that can be permanently rewritten.

[Technical background of the invention and its problems]

For example, the one shown in FIG. 3 is known as an electrically rewritable nonvolatile memory having a floating gate.

FIG. 3(a) is a plan view, and FIG. 3(b) and (C) are sectional views taken along line AA' and line BB' in FIG. 3(a), respectively. P
n middle layer (121) formed on a type silicon substrate (11)
(122), these n middle layers (121)*(122
) and a control gate (14) stacked on the floating gate (13) with an insulating film interposed between them. Between (122), (123) and these n-middle layers (122) and (123), a selection transistor is formed by a gate electrode haze formed through a Sa film.Rewriting of the memory contents is possible in the n-middle layer. The floating gate 1L3t-
This is done by extending the floating gate U and receiving and receiving charges between the N middle layer (124). H is a field insulating film.

In a memo IJ) transistor with such a structure.

Since electrons are injected and emitted between the n-middle layer (124) and the floating gate u3), it has been difficult to miniaturize the tunnel insulating film 7). Therefore, under writing conditions, there is a limit to the realization of an element that allows high-speed rewriting with a low pulse voltage, and there is also a limit to miniaturization of the memory element itself. Furthermore, in order to improve memory retention, it is desirable that the tunnel region be small.

[Purpose of the invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a memory element that has a smaller tunnel region, can be rewritten at higher speed, is suitable for miniaturization of the element, and improves memory retention.

[Summary of the invention]

In the present invention, for example, as shown in FIG. 1, a protrusion αe extends along the sidewall via the tunnel insulating film αIy &: left on the sidewall of the floating gate αj, and this protrusion (1e) extends from the n middle layer ( 122).Electrons are exchanged through the tunnel insulating film fl on the side wall of the floating gate (13).
Since the area occupied by the tunnel region depends on the film thickness of the floating gate AS, the tunnel region can be reduced. Therefore, due to the electric field concentration caused by the reduction of the tunnel region, high-speed rewriting is possible with a low write voltage. ! Since the tunnel oxide film (L1) extends perpendicularly to the P-type silicon substrate (iυ), the area occupied by the tunnel insulating film U in the memory element becomes extremely small, making it suitable for miniaturization of the memory element.

〔Effect of the invention〕

According to the present invention, since the tunnel region can be localized, the electric field concentration associated with it can be reduced, the rewriting speed can be increased with a lower voltage than the conventional write conditions, and the memory retention characteristics can be increased. Furthermore, since the tunnel region extends perpendicularly to the silicon substrate, the memory element can be miniaturized.

[Embodiments of the invention]

Next, the present invention is shown in FIGS. 1(a), (b) and 2(a) to (d). As shown in Figure 2(a),
For example, an oxide film η is grown for 30 CIA on the entire exposed silicon surface on a Pa silicon substrate, and on top of that, a gate electrode (L51) and a floating gate (L3t) of a selection transistor made of polycrystalline silicon are grown by vapor phase growth. -Mask material o
1) into the desired shape. The bet is field insulation. Next, as shown in (b), an oxide film of, for example, 200 Å is formed on the surface, and anisotropic etching (reactive ion etching method) is performed to form the gate electrode α9 and the floating gate 1.
The oxide film is removed except for the sidewalls of the base. Next, as shown in (C), a polycrystalline silicon layer (2G') is deposited on the surface and phosphorus is diffused. (123) is formed.

Next, anisotropic etching (reactive ion etching method)
The polycrystalline silicon is removed, leaving behind the gate electrode haze and the side wall of the floating gate a3. At this time, the n middle layer (122
) to form a friend protrusion ue.

The polycrystalline silicon remaining on the side walls of the other gate electrode α9 and the floating gate Q3 is removed by isotropic etching (dry etching method) after masking the protrusion 1e with a mask material (5). ). Thereafter, as is well known, a control gate made of polycrystalline silicon is laminated by vapor phase growth to form an element.

In this element, for example, electrons are injected when the n middle layer (122) is o2 and the control gate I capacitively coupled to the floating gate is 20V, and electrons are emitted and erased when the voltage is 20V and OV, respectively. Injection and emission occur only in the tunnel insulating film on the side wall of the floating gate, and its area is small, providing high retention performance and effective for high-speed rewriting due to electric field concentration.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are plan views and sectional views for explaining the present invention in detail, and FIGS. 2(a) to (d) are the present invention.
A cross-sectional view showing the embodiment, FIG. S (a) is a plan view for explaining a conventional example, and FIGS. In the figure, 11...P-type silicon substrate, 13...
floating gate, 14... control gate, 15... gate electrode, 16... protrusion, 17... gate insulating film, 1
8... Field insulating film, 19... Tunnel oxide film, 20... Polycrystalline silicon thin film, 21... Mask material,
121-124...n middle layer. Agent Patent attorney Kensuke Norichika (and one other person) Figure 1 (d) Figure 2 (α) Figure

Claims (1)

[Claims] In an electrically rewritable nonvolatile semiconductor memory device having a floating gate and a control gate capacitively coupled to the floating gate, a highly concentrated impurity region of a conductivity type opposite to that of the semiconductor substrate formed on the surface of the semiconductor substrate is provided. A conductive protrusion extends along the side wall of the floating gate via a tunnel insulating film, and charge is transferred to and from the floating gate via the tunnel insulating film. A non-volatile semiconductor memory device characterized by: