JPH03280580A - Semiconductor storage device and its manufacture - Google Patents
Semiconductor storage device and its manufactureInfo
- Publication number
- JPH03280580A JPH03280580A JP2082439A JP8243990A JPH03280580A JP H03280580 A JPH03280580 A JP H03280580A JP 2082439 A JP2082439 A JP 2082439A JP 8243990 A JP8243990 A JP 8243990A JP H03280580 A JPH03280580 A JP H03280580A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- gate electrode
- insulating film
- silicon oxide
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000009792 diffusion process Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 229910052785 arsenic Inorganic materials 0.000 abstract description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 3
- 125000004437 phosphorous atom Chemical group 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 229910052698 phosphorus Inorganic materials 0.000 abstract 1
- 239000011574 phosphorus Substances 0.000 abstract 1
- 230000005641 tunneling Effects 0.000 description 5
- 230000001133 acceleration Effects 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- UOCLXMDMGBRAIB-UHFFFAOYSA-N 1,1,1-trichloroethane Chemical compound CC(Cl)(Cl)Cl UOCLXMDMGBRAIB-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、フローティングゲート型の電界効果トランジ
スタで構成される半導体記憶装置およびその製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device composed of floating gate field effect transistors and a method of manufacturing the same.
従来の技術
従来、電気的書き込み消去が可能なＥＥＰＲＯＭ（Ｅｌ
ｅｃｔｒｉｃａｌｌｙ Ｅｒａｓａｂｌｅ ａｎｄ
ＰｒｏｇｒａｍａｂｌｅＲＯＭ）の一つとして、ト
ンネリング注入により書き込み消去を行うフローティン
グゲート構造の半導体記憶装置がよ（知られている。こ
のフローティングゲート構造の半導体記憶装置は、拡散
層上の薄い絶縁膜を介して電荷のトンネリング注入を行
い、薄い絶ｔ１１ＩＩＩ上のフローティングゲート電極
に電荷を蓄積させ、トランジスタのしきい値電圧を変化
させて情報を記憶させることを原理としている。BACKGROUND OF THE INVENTION Conventionally, EEPROM (El
electrically Erasable and
A semiconductor memory device with a floating gate structure that performs writing and erasing by tunneling injection is known as one type of programmable ROM (Programmable ROM). In this semiconductor memory device with a floating gate structure, charges are transferred through a thin insulating film on a diffusion layer. The principle is that tunneling injection is performed to accumulate charge in the floating gate electrode on the thin transistor T11III, and information is stored by changing the threshold voltage of the transistor.
以下に従来の半導体記憶装置について説明する。A conventional semiconductor memory device will be explained below.
第２図は従来のフローティングゲート型の半導体記憶装
置の要部断面図である。第２図に示すように、Ｐ型シリ
コン基板２１の中にＮ型拡散層からなるソース領域２２
およびドレイン領域２３が形成され、ソース領域２２お
よびドレイン領域２３にまたがって比較的厚い酸化シリ
コン膜２４が形成されるとともに、この酸化シリコン８
Ｉ２４の一部分のみを開孔し、この開孔部にトンネリン
グ媒体となる薄い酸化シリコン膜２５が形成され、酸化
シリコン膜２４および２５の上にフローティングゲート
電極２６．酸化シリコン膜２７およびコントロールゲー
ト電極２８が順次積層された構造となっている。FIG. 2 is a sectional view of a main part of a conventional floating gate type semiconductor memory device. As shown in FIG. 2, a source region 22 made of an N-type diffusion layer is formed in a P-type silicon substrate 21.
and a drain region 23 are formed, and a relatively thick silicon oxide film 24 is formed spanning the source region 22 and drain region 23.
Only a portion of I24 is opened, a thin silicon oxide film 25 serving as a tunneling medium is formed in this opening, and a floating gate electrode 26 is formed on the silicon oxide films 24 and 25. It has a structure in which a silicon oxide film 27 and a control gate electrode 28 are sequentially laminated.
従来、第２図のようなフローティングゲート型の半導体
記憶装置を製造する場合、通常Ｐ型シリコン基板２１の
表面上に、Ｎ型拡散層２２，３、酸化シリコン膜２４，
５、フローティングゲート電極２６．酸化シリコン膜２
７．コ〉・トロールゲート電極２８を順次積層していた
。Conventionally, when manufacturing a floating gate type semiconductor memory device as shown in FIG. 2, N-type diffusion layers 22, 3, silicon oxide film 24,
5. Floating gate electrode 26. Silicon oxide film 2
7. Control gate electrodes 28 were sequentially laminated.
発明が解決しようとする課題
しかしながら、上記の従来の構成では、フローティング
ゲート型の半導体記憶装置のコントロールゲート電極２
８と７０−ティングゲート電極２６とは酸化シリコン膜
２７の介在により容量結合されているため、コントロー
ルゲート電極２８による消去および書き込みを効率的か
つ高速に行うためにはコントロールゲート電極２８とフ
ローティングゲート電極２６との間の酸化シリコン膜２
７を薄くするか、コントロールゲート電極２８の面積を
大きくする必要がある。しかし、２つの電極間の酸化シ
リコン８１１２７には書き込みおよび消去時に高い電圧
が印加されるため、信頼性上の問題から膜厚を薄くする
ことはできない。このため、高速な書き込みおよび消去
を行うためにはコントロールゲート電極２８の面積を太
き（する必要があり、メモリセルの面積が大きくなるた
め高集積化が困難であるという課題を有していた。Problems to be Solved by the Invention However, in the above conventional configuration, the control gate electrode 2 of the floating gate type semiconductor memory device
Since the 8- and 70-ting gate electrodes 26 are capacitively coupled through the silicon oxide film 27, in order to perform erasing and writing using the control gate electrode 28 efficiently and at high speed, the control gate electrode 28 and the floating gate electrode must be connected. silicon oxide film 2 between
It is necessary to make the electrode 7 thinner or to increase the area of the control gate electrode 28. However, since a high voltage is applied to the silicon oxide 81127 between the two electrodes during writing and erasing, the film thickness cannot be reduced due to reliability issues. Therefore, in order to perform high-speed writing and erasing, it is necessary to increase the area of the control gate electrode 28, which increases the area of the memory cell, making it difficult to achieve high integration. .
本発明は、上記従来の課題を解決するもので、高速動作
および高集積化を実現するフローティングゲート構造の
半導体記憶装置およびその製造方法を提供することを目
的とする。The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor memory device with a floating gate structure that achieves high-speed operation and high integration, and a method for manufacturing the same.
課題を解決するための手段
この目的を達成するために本発明の半導体記憶装置は、
半導体基板に設けたトレンチの底部に他方導電型のドレ
イン領域を、半導体基板の表面トレンチ近傍に他方導電
型のソースｆＲ域を備え、トレンチ底部のドレイン領域
の一部にトンネリング媒体となる薄い絶縁膜を設けたメ
モリセルトランジスタおよびドレイン領域Ａ域を共通に
した選択トランジスタとからなる構成を有している。Means for Solving the Problems In order to achieve this object, the semiconductor memory device of the present invention comprises:
A drain region of the other conductivity type is provided at the bottom of a trench provided in the semiconductor substrate, a source fR region of the other conductivity type is provided near the surface trench of the semiconductor substrate, and a thin insulating film serving as a tunneling medium is provided at a part of the drain region at the bottom of the trench. It has a configuration consisting of a memory cell transistor provided with a memory cell transistor and a selection transistor having a common drain region A.
作用
この構成によってフローティングゲート電極およびコン
トロールゲート電極の大部分はトレンチの底部および側
壁部に形成されるため、コントロールゲート電極の面積
が従来の平面上に形成されたメモリセルトランジスタの
コントロールゲート電極の面積より大きく取ることがで
き、コントロールゲート電極とフローティングゲート電
極との容量が増大する。また、フローティングゲート電
極およびコントロールゲート電極がトレンチの一方の側
壁部に形成され、かつメモリセルトランジスタを選択す
るための選択トランジスタが他方の側壁部に形成される
ため、メモリセルトランジスタの二次元的な占有面積を
従来の平面型に比べて縮小することができる。したがっ
て、結合容量の増大に伴いコントロールゲート電極にょ
るＩｌｌ Ｉ’ｌｌ効率が向上し、フローティングゲー
トへの書き込みまたは消去の速度が向上する。Effect: With this configuration, most of the floating gate electrode and control gate electrode are formed on the bottom and sidewalls of the trench, so the area of the control gate electrode is smaller than that of the conventional control gate electrode of a memory cell transistor formed on a flat surface. It can be made larger, increasing the capacitance between the control gate electrode and the floating gate electrode. Furthermore, since the floating gate electrode and the control gate electrode are formed on one side wall of the trench, and the selection transistor for selecting the memory cell transistor is formed on the other side wall, the two-dimensional The occupied area can be reduced compared to the conventional planar type. Therefore, as the coupling capacitance increases, the Ill I'll efficiency of the control gate electrode improves, and the writing or erasing speed of the floating gate increases.
実施例
以下本発明にかかる半導体記憶装置の一実施例について
、図面を参照しながら説明する。Embodiment Hereinafter, an embodiment of a semiconductor memory device according to the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本実施例の製造工程順断面図で
ある。図において、１はＰ型半導体基板、２はトレンチ
、３はトレンチ底部、４はドレイン領域、５は酸化シリ
コン膜、６は薄い酸化シリコン膜、７は７０−ティング
ゲート電極、８は選択トランジスタのゲート電極、９は
酸化シリコン膜、１０はコントロールゲート電極、１１
はソース領域である。FIGS. 1(a) to 1(d) are sectional views in the order of manufacturing steps of this embodiment. In the figure, 1 is a P-type semiconductor substrate, 2 is a trench, 3 is a trench bottom, 4 is a drain region, 5 is a silicon oxide film, 6 is a thin silicon oxide film, 7 is a 70-ting gate electrode, and 8 is a selection transistor. Gate electrode, 9 is a silicon oxide film, 10 is a control gate electrode, 11
is the source area.
以下第１図に沿って本発明の一実施例における半導体記
憶装置の製造方法を説明する。A method of manufacturing a semiconductor memory device according to an embodiment of the present invention will be described below with reference to FIG.
まず、第１図（ａ）に示すように比抵抗５〜ｌｏΩＣ−
のＰ型シリコン基板１上に幅１．５×長さ１００＃１ｍ
で深さ３μ−のトレンチ２を反応性イオンエツチング（
ＲＩＥ方式）によるドライエツチング技術により形成す
る。このトレンチの底部３およびＰ型シリコン基板ｌの
表面上の所定の位置にフォトリソグラフィー技術により
形成したレジストパターンをマスクとして砒素を注入量
ｌ×１０目／ｃｊ、加速電圧１４０ｋｅＶで注入し、そ
の後９００℃の温度の窒素雰囲気中で３０分間アニール
を行い。First, as shown in Figure 1(a), the specific resistance is 5~loΩC-
Width 1.5 x length 100#1m on P-type silicon substrate 1
Reactive ion etching (
It is formed using a dry etching technique (RIE method). Using a resist pattern formed by photolithography as a mask, arsenic was implanted at predetermined positions on the bottom 3 of the trench and on the surface of the P-type silicon substrate l at an implantation amount of l×10/cj at an acceleration voltage of 140 keV, and then at an acceleration voltage of 140 keV. Annealing was performed for 30 minutes in a nitrogen atmosphere at a temperature of .degree.
ソース領域１１およびドレイン領域４となる拡散層を形
成する。この時、最終的にソース領域１１となる領域に
も砒素が注入される。次に同図（ｂ）に示すように、９
００Ｙ：の温度の水蒸気雰囲気中でＰ型シリコン基板１
の表面およびトレンチ内部に酸化シリコン８１５を５Ｏ
ｎ−形成する。さらにこの酸化シリコン膜５のトレンチ
底部３の所定の領域に開孔部を形成し、９００℃で２モ
ル％のトリクロロエタンを含む水蒸気雰囲気中でトンネ
リング媒体となる薄い酸化シリコン膜６を形成する。次
に同図（Ｃ）に示すように減圧ＣＶＤ法により燐原子を
３ Ｘ ｌ Ｏ”／ｃｊ含む多結晶シリコン膜を３０Ｏ
ｎ−の厚さに堆積し、フォトリソグラフィー技術により
パターン形成をし、フローティングゲート電極７および
選択トランジスタのゲート電極８を形成する。次に同図
ω）に示すように、１１５０℃の温度の酸素雰囲気中で
ランプ加熱による急速酸化法によりフローティングゲー
ト電極７上に４５ｎ−の酸化シリコン１ＩＩ９を形成し
、減圧ＣＶＤ法により燐原子を３ Ｘ １０”／ ｃｗ
ｔ含んだ多結晶シリコン膜を２００ｎａ＋形成し、フォ
トリソグラフィー技術によりパターン形成を行い、フロ
ーティングゲートを極７の上に酸化シリコン！１ｌｉ９
を介してコントロールゲート電極ｌＯを形成する。その
後、砒素を注入量２ Ｘ １０１５／ｃｊ、加速電圧４
０ｋｅＶでイオン注入し、メモリセルおよび選択トラン
ジスタのソース領域１１を形成する。Diffusion layers that will become the source region 11 and drain region 4 are formed. At this time, arsenic is also implanted into the region that will eventually become the source region 11. Next, as shown in the same figure (b), 9
P-type silicon substrate 1 in a steam atmosphere at a temperature of 00Y:
5O silicon oxide 815 on the surface and inside the trench.
n- form. Further, an opening is formed in a predetermined region of the trench bottom 3 of this silicon oxide film 5, and a thin silicon oxide film 6 that becomes a tunneling medium is formed at 900° C. in a water vapor atmosphere containing 2 mol % trichloroethane. Next, as shown in the same figure (C), a polycrystalline silicon film containing phosphorus atoms of 300
It is deposited to a thickness of n- and patterned by photolithography to form the floating gate electrode 7 and the gate electrode 8 of the selection transistor. Next, as shown in ω) in the same figure, 45n- silicon oxide 1II9 is formed on the floating gate electrode 7 by a rapid oxidation method using lamp heating in an oxygen atmosphere at a temperature of 1150°C, and phosphorus atoms are removed by a low pressure CVD method. 3 x 10”/cw
A polycrystalline silicon film containing 200 na+ is formed, patterned using photolithography, and a floating gate is formed on the electrode 7 using silicon oxide! 1li9
A control gate electrode IO is formed through the . After that, arsenic was implanted at a dose of 2 x 1015/cj and an acceleration voltage of 4
Ion implantation is performed at 0 keV to form source regions 11 of memory cells and selection transistors.
なお、本発明の一実施例における半導体記憶装置の要部
は第１図（ｄ）に示す通り、壁部にフローティングゲー
トを有するメモリセルトランジスタとメモリセルトラン
ジスタを選択する選択トランジスタとが同特に形成され
ており、メモリセルトランジスタと選択トランジスタの
ドレイン領域はトレンチ底部で共通となっている。As shown in FIG. 1(d), the main part of the semiconductor memory device according to an embodiment of the present invention includes a memory cell transistor having a floating gate on a wall portion and a selection transistor for selecting the memory cell transistor. The drain regions of the memory cell transistor and the selection transistor are common at the bottom of the trench.
発明の効果
以上のように、本発明によれば、メモリセルトランジス
タの占有面積を小さ（するとともにコントロールゲート
電極とフローティングゲート電極との間の結合容量を増
大させることができ、高栗積化、大容量化および高速化
を可能にする優れた半導体記憶装置およびその製造方法
を実現するものである。Effects of the Invention As described above, according to the present invention, the area occupied by the memory cell transistor can be reduced (and the coupling capacitance between the control gate electrode and the floating gate electrode can be increased), and the area of the memory cell transistor can be increased. The present invention aims to realize an excellent semiconductor memory device and a method for manufacturing the same that enable larger capacity and higher speed.
第１図（ａ）〜（ｄ）は本発明の一実施例における半導
体記憶装置の製造工程順断面図、第２図は従来の半導体
記憶装置の要部断面図である。
１・・・・・・Ｐ型半導体基板（半導体基板）、２・・
・・・・トレンチ、３・・・・・・トレンチ底部、４・
・・・・・ドレイン領域（第１の拡散領域）、５・・・
・・・酸化シリコン膜（第１の絶縁膜）、６・・・・・
・薄い酸化シリコン膜（第２の給１１．７・・・・・・
）ａ−ティングゲート電極（第１のゲート電極）、８・
・・内選択トランジスタのゲート電極（第３のゲート電
極）、９・旧・・酸化シリコンＩＩ（第３の絶縁膜）、
１ｏ・・・・・・コントロールゲート電極（第２のゲー
ト電極）、１１・・・・・・ソースミＲ域（第２の拡散
領域）。FIGS. 1(a) to 1(d) are sectional views in the order of manufacturing steps of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a sectional view of essential parts of a conventional semiconductor memory device. 1...P-type semiconductor substrate (semiconductor substrate), 2...
...Trench, 3...Trench bottom, 4.
...Drain region (first diffusion region), 5...
...Silicon oxide film (first insulating film), 6...
・Thin silicon oxide film (second supply 11.7...
) a-ting gate electrode (first gate electrode), 8.
...Gate electrode of the selection transistor (third gate electrode), 9.Old...Silicon oxide II (third insulating film),
1o... Control gate electrode (second gate electrode), 11... Source MiR region (second diffusion region).
Claims (2)
のトレンチの底部に設けた他方導電型の第１の拡散領域
と、半導体基板上でトレンチの両側に近接して設けた他
方導電型の第２の拡散領域と、半導体基板の表面および
トレンチの側壁部と底部を覆って設けた第１の絶縁膜と
、第１の拡散領域上で第１の絶縁膜に形成された開口部
に設けた薄い第２の絶縁膜と、開口部上を含みトレンチ
の一方の側壁部に設けた第１のゲート電極と、第１のゲ
ート電極上に第３の絶縁膜を介して設けた第２のゲート
電極と、トレンチの他方の側壁部に第１の絶縁膜を介し
て設けた第３のゲート電極とを備えた半導体記憶装置。(1) A trench provided in a semiconductor substrate of one conductivity type, a first diffusion region of the other conductivity type provided at the bottom of the trench, and a first diffusion region of the other conductivity type provided close to both sides of the trench on the semiconductor substrate. a second diffusion region, a first insulating film provided to cover the surface of the semiconductor substrate and the sidewalls and bottom of the trench; and a first insulating film provided in an opening formed in the first insulating film over the first diffusion region. a thin second insulating film, a first gate electrode provided on one side wall of the trench including over the opening, and a second gate electrode provided on the first gate electrode with a third insulating film interposed therebetween. A semiconductor memory device comprising a gate electrode and a third gate electrode provided on the other side wall of a trench with a first insulating film interposed therebetween.
程と、他方導電型の第１の拡散領域をトレンチの底部に
、他方導電型の第２の拡散領域を半導体基板上のトレン
チに近接した領域にそれぞれ形成する工程と、半導体基
板の表面とトレンチの側壁部とを覆う第１の絶縁膜を形
成する工程と、第１の拡散領域上の第１の絶縁膜の開口
部を設けその開口部に薄い第２の絶縁膜を形成する工程
と、開口部上を含みトレンチの一方の側壁部から半導体
基板の表面に第１のゲート電極を、トレンチの他方の側
壁部から半導体基板の表面にかけて第２のゲート電極を
それぞれ形成する工程と、第１のゲート電極上に第３の
絶縁膜を介して第２のゲート電極を形成する工程とを備
えた半導体記憶装置の製造方法。(2) A step of forming a trench in a semiconductor substrate of one conductivity type, a first diffusion region of the other conductivity type at the bottom of the trench, and a second diffusion region of the other conductivity type close to the trench on the semiconductor substrate. forming a first insulating film covering the surface of the semiconductor substrate and the sidewalls of the trench, and forming an opening in the first insulating film over the first diffusion region. a step of forming a thin second insulating film on the opening, and a step of forming a first gate electrode from one sidewall of the trench to the surface of the semiconductor substrate including over the opening, and from the other sidewall of the trench to the surface of the semiconductor substrate. A method for manufacturing a semiconductor memory device, comprising the steps of forming second gate electrodes respectively, and forming the second gate electrodes on the first gate electrodes with a third insulating film interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2082439A JPH03280580A (en) | 1990-03-29 | 1990-03-29 | Semiconductor storage device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2082439A JPH03280580A (en) | 1990-03-29 | 1990-03-29 | Semiconductor storage device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03280580A true JPH03280580A (en) | 1991-12-11 |
Family
ID=13774575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2082439A Pending JPH03280580A (en) | 1990-03-29 | 1990-03-29 | Semiconductor storage device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03280580A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5486714A (en) * | 1994-07-18 | 1996-01-23 | United Microelectronics Corporation | Trench EEPROM with tunnel oxide in trench |
| US5606521A (en) * | 1995-06-28 | 1997-02-25 | Philips Electronics North America Corp. | Electrically erasable and programmable read only memory with non-uniform dielectric thickness |
| US6541815B1 (en) * | 2001-10-11 | 2003-04-01 | International Business Machines Corporation | High-density dual-cell flash memory structure |
| WO2002073698A3 (en) * | 2001-03-08 | 2003-06-19 | Micron Technology Inc | A 2f2 memory device system and method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03185764A (en) * | 1989-12-14 | 1991-08-13 | Nec Corp | Mos type non-volatile semiconductor memory device |
-
1990
- 1990-03-29 JP JP2082439A patent/JPH03280580A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03185764A (en) * | 1989-12-14 | 1991-08-13 | Nec Corp | Mos type non-volatile semiconductor memory device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5486714A (en) * | 1994-07-18 | 1996-01-23 | United Microelectronics Corporation | Trench EEPROM with tunnel oxide in trench |
| US5606521A (en) * | 1995-06-28 | 1997-02-25 | Philips Electronics North America Corp. | Electrically erasable and programmable read only memory with non-uniform dielectric thickness |
| WO2002073698A3 (en) * | 2001-03-08 | 2003-06-19 | Micron Technology Inc | A 2f2 memory device system and method |
| US6759707B2 (en) | 2001-03-08 | 2004-07-06 | Micron Technology, Inc. | 2F2 memory device system |
| CN100341153C (en) * | 2001-03-08 | 2007-10-03 | 微米技术公司 | 2f2 memory device system and method |
| US6541815B1 (en) * | 2001-10-11 | 2003-04-01 | International Business Machines Corporation | High-density dual-cell flash memory structure |
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