JPS6159879A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a gate resistance by implanting ions to a GaAs substrate, then annealing with a silicon oxide film as a cap, removing a silicon oxide film, then performing a plasma etching including fluorine, and depositing a high melting point metal to form a gate. CONSTITUTION:With photoresist 2 patterned on a GaAs semi-insulating substrate 1 as a mask silicon is as ion stream 3 to form an ion implanted portion 4. Then photoresist 2 is removed, a silicon oxide film 5 is formed, and annealed in hydrogen atmosphere. Then, the portion 4 becomes an N type active portion 4a. Then, after a silicon oxide film 5 is removed, it is etched by carbon fluoride plasma 21. Then, a surface modified layer is removed, rhenium is deposited as high melting point metal on the overall surface, and a gate mask 7 is formed of a photoresist. Then, a gate 6 is formed by plasma etching. Similarly, ions are implanted to form an n<+> type active portion 10a, and the electrode 12 of the multilayer structure of AuGe/Ni/Au is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a gallium field effect transistor (hereinafter referred to as GaAFE) using a high melting point metal as a gate material.
The present invention relates to a method for manufacturing a semiconductor device that can be used to form a gate (abbreviated as T).

Conventional structure and its problems In recent years, gallium arsenide (GaAs) has been replaced by silicon (SL).
It has attracted attention as a next-generation semiconductor device to replace silicon because it has a large bandgap compared to silicon and can produce a semi-insulating substrate, and its electron mobility is 5 to 6 times higher. , Cell 7 using high melting point metal as a method to reduce parasitic resistance of GaAsFET
GaAsFETs are made by alignment.

Hereinafter, a conventional method for manufacturing a semiconductor device will be described with reference to the drawings. Figure 1 a, b, c.

d, e, 1. q is a process cross-sectional view of a conventional semiconductor device manufacturing method, in which 1 is a gallium arsenide semi-insulating substrate, 2 is a first photoresist that serves as a mask during the first selective ion implantation for forming an active layer, and 3 is a process cross-sectional view of a conventional semiconductor device manufacturing method. 4 is a primary ion implantation part formed by the primary ion flow 3, and 5 is a primary ion implantation part for fully activating the primary ion implantation part. 4a is the n active region activated by the first annealing, 6 is a gate made of a high melting point metal, and 7 is the gate. Gate mask used to form 6, 8 is GaAa formed by self-line
A second photoresist serving as a mask for the secondary ion flow e that forms the source and drain of the FET, 1
o is a secondary ion implantation region formed by the secondary ion flow 9; 11 is a secondary ion implantation region 11 which serves as a cap when performing secondary annealing to activate the secondary ion implantation region 10; Silicon oxide film, 10a is n+ active part activated by the second annealing, 12 is GaAgFET
source and drain electrodes.

A method of manufacturing a conventional semiconductor device configured as described above will be described below. First, a first selective ion implantation process for forming an active layer on a gallium arsenide semi-insulating substrate 1 is performed.
First photoresist 2f as a mask for the next ion flow 3
Patterning is carried out (FIG. 1a). Next, first selective ion implantation is performed using silico/ as the first ion flow 3 to form an active layer (FIG. 1b). Furthermore, in order to activate the primary ion implantation part 4, the first photoresist 2 is
After removing the first silicon oxide film 5, a first silicon oxide film 5 is formed as a cap, and first annealing is performed for about 850'CI5 minutes (FIG. 1C). Note that the first cap is made of arsenic (
This prevents As) from scattering. Next, after removing the first silicon/oxide film using a hydrofluoric acid buffer (hereinafter abbreviated as BHF), a high melting point metal (W, etc.) is deposited on the entire surface, and the gate is etched by dry etching containing fluorine using a gate mask. 6
(Fig. 1d). Furthermore, GaAg FET
In order to reduce the parasitic resistance at the source and drain of the ion beam, as shown in FIG. A 10ft injection section is formed.

Next, the second photoresist 8 and the gate mask 7
After removing n
An active part 10a is formed (FIG. 1f). Furthermore, the second
Next, the silicon oxide film 11 is removed using the BHF, and the source and
Forming the drain electrode 12 (FIG. 1q) o As described above, since the n+ active region 10a can be formed by the self-alignment using the gate 6, the source/drain electrode 12 is formed as shown in FIG. 1q. Although the effective source and drain are formed away from the gate,
Since it is the active part 10a, the parasitic resistance can be significantly reduced.

However, in the above method, a high melting point pot is used as the gate material because it reacts with gallium arsenide when sealing the gate 6 of the GaAs FET after the second annealing. Due to the difference in thermal expansion coefficient between high-melting point metal and gallium arsenide, it is easy to peel off, causing a gate? The drawback was that it could not be made thicker. Gate thickness h(
d1 in FIG. 1 contributes to the gate resistance of the GaAs FET, and if the thickness h of the gate is thin, the gate resistance increases, which prevents the characteristics of the GaAs FET from improving. For example, in the case of tungsten (W),
In the conventional method, when the thickness h of the gate exceeds about 1000 Ae, peeling tends to occur. Therefore, the gate resistance is gate length 1
Assuming that the gate thickness is 1000 μm, the specific resistance of tungsten is 5.64×10 Ω, and the gate width is 100 μm.
It comes to about 670.

OBJECTS OF THE INVENTION An object of the present invention is to make it possible to form a high melting point metal that becomes the gate of a GaAg FET to be thicker than before,
The object of the present invention is to provide a method for manufacturing a semiconductor device that improves the characteristics of the GaAs FET.

Structure of the Invention The method for manufacturing a semiconductor device of the present invention includes the steps of implanting desired selective ions into a gallium arsenide semi-insulating substrate when forming a gate of a GaAsFET, and annealing the selective ion implantation using a silicon oxide film as a cap. a step of removing the silicon oxide film and then performing dry etching using plasma containing fluorine; a step of vapor depositing a high melting point metal to form the gate gold; This makes it possible to form the high-melting point metal that serves as the gate of the GaAsFET at least 1.5 to 2 times thicker than before, thereby reducing the gate resistance of the GaAsFET and improving the characteristics of the GaAsFET. .

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIGS. 2a, b, c, d, e, f, g, and h are process cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. In FIG. 2, 1 is a gallium arsenide semi-insulating substrate, 2 is a first photoresist that serves as a mask during the first selective ion implantation for forming an active layer, and 3 is a first photoresist for forming an active layer. /flow, 4 is a primary ion implantation part formed by the primary ion flow 3, and 5. 4a is the first silicon oxide film that becomes the cap during the first annealing, and
21 is a plasma containing fluorine; 6 is a gate made of a high melting point metal; 7 is a gate mask for forming the gate gold; 8 is a mask for the secondary ion flow 9 2nd photoresist, 1o
11 is a secondary ion implantation part formed by the secondary ion flow 9, and 11 is a secondary ion implantation part that serves as a cap when performing a second annealing to activate the secondary ion implantation part 1o. Silicon oxide film, 10a is n+ active part activated by the second annealing, 12 is G a A 5F
These are the source and drain electrodes of the ET.

A method of manufacturing the semiconductor device of this embodiment configured as described above will be described below. First, on a gallium arsenide semi-insulating substrate 1, a photoresist 2 is patterned to a thickness of about 1 μm using photolithography, which will serve as a mask during the first selective ion implantation to form an active layer of a GaAsFET (second Diagram a). Next, using the 7-oto-resistor 2 as a mask, the silicon is made into an ion flow 3, the accelerating electric field is 120 KeV, and the implantation dose is 4, 7X1012dose.
First selective ion implantation is performed as Ayi to form the first ion implantation part 4 (FIG. 2b). Next, the photoresist 2 is removed with an organic solvent, and in order to activate the silicon implanted in the first selective ion implantation, a first silicon oxide film is formed using a low pressure CVD method at a substrate temperature of 320°C. After forming approximately 2,000 pieces of No. 5, a first annealing was performed for 20 minutes in a hydrogen atmosphere at 850° C. (FIG. 2C).

By the first annealing, the first ion implantation part 4 becomes an n active part 4a. - Next, the first silicon oxide film was heated with hydrofluoric acid (47wt%) and ammonium fluoride aqueous solution (40Wt%) with a capacity of 1:5 BHF (hereinafter 1:
After removal using 5Bl (abbreviated as F), the flow rate of fluorocarbon was adjusted to 3° SCCM by fluorocarbon plasma 21.
Dry etching was performed for 2 minutes at a pressure of 300 mTorr and an RF power of 50 W (no second symbol was observed. Next, the surface was immersed in the 1:5 BHF for about 6 seconds again to remove the surface modified layer caused by the dry etching. Then, to further remove the surface oxide layer, the substrate was immersed in hydrochloric acid (18 wt%) for 1 minute and washed with running AV pure water. Rhenium (Re) was used as a zero-order high melting point metal using an electron beam method, and the substrate temperature was kept at a total temperature of 100%. 'C, the vacuum level is 3 x 10" Torr or less, and the entire surface is vapor deposited to a thickness of 2,500 mm. Furthermore, a gate mask of 7 ft. and a thickness of approximately 7,000 mm, which will be used as a mask during the etching of the rhenium, is formed using photo phosphorography. Next, the rhenium gate 6 is formed using the gate mask 7 by dry etching using fluorocarbon plasma.
'lt is formed (Fig. 2e). Thereafter, similarly to the conventional example, after forming a second photoresist 8 by photolithography, using the second photoresist 8, the gate 6, and the gate mask 7 as masks, GaAS
In order to reduce the parasitic resistance at the source and drain of the FET, the silicon is used as a secondary ion current 9 and the accelerating electric field is set to 15
0KeV, implantation amount 1×1014dOBe/c:
Next, selective ion implantation is performed (FIG. 2f). Next, after removing the gate mask 7 and the second photoresist with an organic solution, the second ion implantation region 10 formed by the second ion implantation is activated by the low pressure CVD method. After forming the next silicon oxide film 11, a second annealing is performed for 10 minutes in a hydrogen atmosphere at 800°C.
+Active region 10 a f is formed (FIG. 2q). Further, after removing the second silicon oxide film 11 with the 1:5BHF, the source and drain electrodes 12''f: having a multilayer structure of AuGe/Ni/Au are formed (Fig. 2h). According to this embodiment, rhenium, which is the gate metal, does not peel off even after the second annealing, and the thickness can be increased to a maximum of about 28 mm.
It is possible to fabricate up to 1.00 mm thick, and compared to the conventional gate made of rhenium, which had a thickness of about 16 mm, it can be made about 1.8 times thicker. Tungsten (W), rhenium (Re), rhenium aluminum alloy (Re Af
tx.

0<x<15), the maximum gate that can be formed without peeling when using the conventional semiconductor device manufacturing method and the semiconductor device manufacturing method according to an embodiment of the present invention. The thickness was compared and shown in the table. As is clear from the table, by the method for manufacturing a semiconductor device of the present invention, a gate can be formed with a gate thickness of about 1.6 to 2 times or more, and the gate resistance can be reduced to % to % or less. Ta.

Table, Maximum Gate Thickness Nao, Rhenium, Aluminum Alloy (ReAj! When used as a GaAs FET, a sufficient breakdown voltage could not be obtained as a gate, making it unsuitable as a gate material. Further, in the above embodiment, the gate metal is formed by all-electron beam evaporation, but the gate metal is not limited to the electron beam evaporation method, but any method may be used as long as it can form a thin film of the gate metal. For example, a sputtering method can be used.0 Effects of the Invention As is clear from the above explanation, the present invention provides GaAsF
When forming the gate of ET, there are a step of implanting desired selective ions into a gallium arsenide semi-insulating substrate, a step of annealing the selective ion implantation using a silicon oxide film as a cap, and a step after removing the silicon oxide film. , a step of completely performing dry etching using plasma containing fluorine, and a step of vapor depositing a high melting point metal to completely form the gate, so the high melting point metal that becomes the gate of the GaAr5 FET is It can be formed to be 1.5 to 2.0 times thicker than the GaAs FET, thereby achieving an excellent effect of reducing the gate resistance of the GaAsFET.

This effect improves the characteristics of GaAs FET0.

[Brief explanation of drawings]

FIG. 1 is a process sectional view of a conventional semiconductor device manufacturing method, and FIG. 2 is a process sectional view of a semiconductor device manufacturing method according to an embodiment of the present invention. 1... Gallium arsenide semi-insulating substrate, 2...
・Primary photoresist, 3...Primary ion flow, 4...N active part, 5...Primary silicon oxide film, 6... ...Gate, 7...
・Gate mask, 8...Second photoresist, 9...Second ion flow, 10a...
n+ active part, 11...second silicon oxide film,
12... Source and drain electrodes. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1 Figure 4 Mountain Figure 2 11NF”1

Claims (3)

[Claims] (1) When forming the gate of a gallium arsenide field effect transistor, a step of performing desired selective ion implantation into a gallium arsenide semi-insulating substrate, and a step of annealing the selective ion implantation using a silicon oxide film as a cap; A method for manufacturing a semiconductor device, comprising: after removing the silicon oxide film, performing dry etching using plasma containing fluorine; and depositing a high melting point metal to form the gate. (2) The method for manufacturing a semiconductor device according to claim (1), wherein the plasma is generated from carbon tetrafluoride or carbon trifluoride-hydride. (3) The high melting point metal is tungsten (W), rhenium (
Re) and rhenium-aluminum alloy (ReAl_
2. The method of manufacturing a semiconductor device according to claim 1, wherein x, 0<x<30.