JPS5996770A - Method of producing integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a process for forming a thin insulating layer entirely on a semiconductor substrate, a process for forming a mask layer entirely on the insulating layer, a process for selectively etching the mask layer, and a process for using the entire mask layer as a mask. ,
The present invention relates to a method for counterfeiting an integrated circuit comprising the steps of selectively etching an insulating layer and a further step of etching (and thereby removing a mask layer).

The fabrication of many integrated circuits involves the formation of a relatively thin layer of material, such as a thin oxide layer, on a second material, such as a semiconductor material, and subsequent patterning of the thin layer of material.

Typically, this patterning involves depositing a resist on a thin layer of material, etching the thin layer of material using the patterned resist as an etching mask, and etching the thin layer of material using the patterned resist as an etch mask.
This is then achieved by completely removing the resist using, for example, a solvent or plasma etchant.

Among the information processing devices that undergo such a fabrication process are many MO8 (metal-oxide-semiconductor) integrated circuits (the term integrated circuit is here used to describe multiple interconnected circuits), such as MO8 logic circuits. (Used as a device.) These MO8 integrated circuits (ICs) have multiple MOS
FETs (metal-oxide-semiconductor field effect transistors), each of which has an active surface layer of semiconductor material, a relatively thin gate oxide (GOX) formed on the surface of the active layer.
, comprising a conductive gate, e.g. doped silicon formed on the surface of the GOX, two relatively heavily doped parts 2 of the active layer, the heavily doped parts being on opposite sides of the gate, and which are part of the MOSFET. Complete source and drain configuration.

MOS FET is made of relatively thick electric field oxide (FOX
) and are electrically isolated from each other.

In addition, there are polysilicon runners that extend from selected gates of MO8, FETs to polysilicon electrodes that extend through thin GOXk, called polyconductors, to the sources or drains of other MOSFETs.

Currently, the MOS I C mentioned above is a relatively thin GOX
It is then fabricated to form a relatively thick FOX on the surface of the active layer of the IC.

The relatively thick FOX separates the GOX coated surface area of the active layer called GASAD (gate and source and drain) which is the part to be formed of the MOSFET' (i7).

Polycon is deposited, for example, on organic photoresist '1GOX and FOX, and G on selected GASAD areas.
Open a window in the resist to expose the OX part,
The patterned resist is then used as an etch mask to etch holes through the exposed portions of the GOX down to the underlying active layer. After complete removal of the resist by chemical solvent or plasma chant, the polysilicon layer is GOX and FOX.
Vc deposited and therefore polysilicon (selected GA
1 (on the SAD region) extending through the GOX to the active layer is also deposited. The polysilicon in the window that contacts the active layer is polycon. The deposited layer of polysilicon is then
The polysilicon gate is patterned to form the entire polysilicon gate in the ASAD region, and a thin G is formed from the gate in the GASAD region.
Polysilicon runners are formed that extend through OXk to polyconductors that extend to regions of the active layer (eg, one or both of the source and drain regions) under other selected GASAD regions.

A disadvantage of the fabrication process described above is the fact that thin layers of material, such as thin GOXVC direct resists, are in contact. Thin layers of these materials can therefore be contaminated by the resist and are undesirably reduced in thickness due to the etching function of the chemical solvent or plasma used to remove the resist. The undesirable thickness reduction of thin material layers that occurs during resist removal is significant by % for layers thinner than about 500 angstroms.

According to the present invention, these problems are solved in the integrated circuit fabrication process described above, in which a conductive protective layer is formed on a thin layer before masking layer formation, and a protective layer is formed on a thin It is characterized by a protective layer.

The present invention relates to a new method for fabricating information processing devices, including a thin oxide layer of material (less than about 400 angstroms thick), which is imaged during device fabrication.

(Selected portions of the surface of the thin layer are not coated with the thin layer; the remaining portion of the surface is.) The invention also relates to devices fabricated with this new method. According to the present invention, a device comprising a thin layer of material (described during fabrication of the device) is fabricated by depositing a protective layer of material on the thin layer of material. Alternatively, two or more protective layers are deposited on the thin layer of material. A thin layer of material is then delineated by patterning a protective layer (or layers) of material. This pattern forming process is
Forming a patterned mask layer, such as a patterned resist, on the surface of the protective layer (or layers) and then using the mask layer as an etching mask to remove the protective layer (or layers). This is done by notching multiple layers.

Once patterned, the thin eyebrow of material is then patterned using, for example, the patterned protective layer (or layers) as an etch mask. Alternatively, a patterned electrode layer may be formed, for example by depositing the entire electrode material layer onto a patterned protective layer (or layers). In this manner, electrode material is also deposited in contact with the window and thin 9z layer in the protective layer (or layers) to form a patterned electrode car. The patterned protective layer (or layers) is incorporated into the denomination chair during fabrication, for example.

Among the materials useful for protecting thin material layers, such as thin oxide layers, such as thin layers of silicon oxide, SiO□, is polysilicon.

In accordance with the present invention, a protective polysilicon layer is deposited over the thin layer of material, for example by conventional low pressure chemical vapor deposition techniques. Advantageously, the thickness of the protective polysilicon layer ranges from about 1000 to about 2000 Angstroms. Thicknesses below about 1000 angstroms are not preferred, as pinholes and defects in the protective polysilicon layer are generally very undesirable.

On the other hand, a thickness greater than about 2000 angstroms is also undesirable. Otherwise, such polysilicon requires an undesirably long time to etch through its thickness during patterning of the layer. However, if long etching times are allowed, thicker layers are not excluded.

Other materials useful for protecting thin material layers include refractory metals such as tungsten or molybdenum. The thickness of the protective transition metal layer is from about 500 to about 2000.
A range of Angstroms is advantageous. Thicknesses outside this range are undesirable for the same reasons stated above.

Thicknesses greater than about 20oO Angstroms are not excluded if long etch times are tolerated.

Both the protective layer (or layers) and the underlying thin protective layer (if required) are patterned by conventional techniques such as wet chemical etching, plasma etching, reactive sputter etching. , if, for example, the thin material layer (to be patterned) is an sI02 thin eyebrow and the protective layer is a layer of polysilicon, the polysilicon layer (through the patterned mask layer) is reactive in the C12 plasma. It is easily etched by sputter polysilicon etching without significantly affecting the 5I02 layer. Useful Cβ2 plasmas are generated at flow rates of about 10 to about 20 u/min in parallel plate reactive sputter etching equipment.
12 gases and the total pressure in the reaction vessel is from 5 to about 10
Maintain at millitorr, 0.1 to about 0.4 watts crn
This can be easily done by keeping the power density within the range of 2. The etch rate ratio of the polysilicon layer to the 5102 layer in such a Cβ2 plasma is typically about 30 to 1.

A plasma as described in Sat (using a patterned polysilicon layer as an etching mask) can also be used.
When patterning the 8102 layer, sputter etch the 5i02 layer (useful, sputtering is relatively slow, about 10 angstroms/min or less) (using the entire patterned polysilicon layer as an etch mask). The layer is preferably etched by 5L02 reactive sputter etching in a CHF3' plasma without significantly affecting the polysilicon layer. A useful CHF3 plasma is a KCHF3' plasma in a reactive sputter etcher at a flow rate of about 15 mm and about 2 occZ.
S!02 in such a CHF3 plasma. The etch rate is typically about 500 angstroms/min, 5102
The etch rate ratio of the layer to the polysilicon layer is typically about 50 to 1.

During patterning of polysilicon and SiO□ layer 5I02
The mask layer on the surface of the polysilicon layer does not touch the layer;
Undesired contamination and thickness reduction of the 5I02 layer is thus avoided.

The invention is not limited to any particular information processing device, any particular protective layer, or any particular protected layer. However, for complete ease of understanding, MO8iC using the process of the present invention
The production of is described below.

Referring to FIG.
A MO8IC (very large scale integrated circuit) is fabricated by forming a relatively thin GOX 30 and a relatively thick F'0X40 on the surface of a layer of doped semiconductor material 2o.

A relatively thick FOX 40 separates GOX coated GASAD regions 50 on the surface of layer 20 where the MOS FET is to be formed. For example, if active layer 20 is silicon, GOX 30 and FOX 40 are typically relatively thin 5I02 and thick 5I02 layers, respectively.

FOX 40 is formed, for example, by thermal oxidation of the surface of layer 20. After opening a window in the FOX (by conventional techniques) to expose the GASAD region 50 on the surface of layer 20, GOX 30 is formed, for example, by thermally oxidizing the layer 50 surface again. V (within the scope of the invention)
For LSI MO8ICs, the thickness of 5iO2GOX30 ranges from about 50 to about 400 angstroms, with about 250 angstroms being preferred. The thickness of GOX30 is not preferably less than about 50 angstroms.

This is because the gate threshold voltage (MOSFET
in the current channel of (C1 producing a detectable current MO8
This is because the minimum voltage across the FET gate (minimum voltage across the FET gate) will be very low and the current will be difficult to regulate. On the other hand, thicknesses greater than about 400 angstroms are also undesirable. Because, to adjust the current in the MO8FET current channel,
This is because an undesirably high voltage must be applied between the gates of the MOSFET.

The thickness of SiO2FOX40 of VLSIMO81,C is
The range is from about 3000 to about 4000 angstroms, with about 350 angstroms being preferred. Approximately 3000
Thicknesses below angstroms are not preferred. [Because] the FOX is thick enough to prevent inversion of the underlying silicon and thereby electrical conduction between the two GASAD regions that should be electrically isolated from each other. Thicknesses greater than about 6,000 angstroms are also undesirable.

If not, such FOX would form undesirable high steps, which would make it difficult for fine materials to be coated during subsequent processes, and would make it difficult to remove these high steps (C). This is because it is difficult.

In accordance with the present invention, after the GOX 30 and FOX 40 of the IC are formed, a protective layer 60 of polysilicon is deposited over the GOX and FOX of the IC, as shown in FIG.

For example, polysilicon layer 60 is deposited using conventional low pressure chemical vapor deposition techniques. The purpose of polysilicon layer 60 may be to protect the underlying GOX 30 from any contamination and erosion that may occur during subsequent lithography. The polysilicon layer 60 ranges from about 1000 to about 2
000 angstroms, preferably about 150'0 angstroms. The probability of pinholes and defects in the polysilicon is undesirably high;
Thicknesses below angstroms are not preferred. On the other hand, thicknesses greater than about 2000 angstroms are also undesirable.

This is because such a polysilicon layer requires an undesirably long time to etch through its thickness during the process of etching holes through both the subsequent polysilicon layer 60 and the selected GOX 300. However, if longer etching times are allowed, even thicker layers will not be removed.

By J, M, Moran and D Maydan,
High resolution, steep distribution, resist pattern ``The Bele System Technical Journal (The Be1
l System Technical Journal
l) Volume 58, No. 5, May-June 1979 102
As described on page 7-1036, a patternable mask layer 7, such as a three-step resist,
0 is written onto the polysilicon layer 60 and the mask layer is patterned. That is, the selected 7'vGASAD
A window is opened in the mask layer to expose the polysilicon portion over the GOX of the region. After that, the polysilicon layer 60
through the exposed portion of the active layer 2 and the underlying GOX 30
0, a hole 80 is etched as shown in FIG. The etching of these holes 80 is, for example, C1
This is done by reactive sputter etching the polysilicon layer 60 in a CHF2 plasma (described above) and reactive sputter etching GOX 30 in a CHF3 plasma (described above). The high selectivity of SiO□ to polysilicon in the C12 plasma essentially excludes 5iO2GOX30'ff: from etching by the C12 plasma.
The high selectivity of the CHF3 plasma to silicon 5102 essentially excludes the polysilicon layer 0 and (silicon) active layer 20 from etching by the CHF3 plasma. The mask layer 70 is then removed using a conventional chemical solvent such as H2SO4 or a conventional plasma etch method.

When the above-described or lithographic process is completed, a second layer 90 of polysilicon is deposited over the first layer 60, so that polysilicon is also deposited in the holes 80 and in contact with the active layer 20. .

Selected: active layer 2 under rv G A S A D region
It is the polysilicon in the hole 80 that contacts layer 20 that constitutes the polycon 100 to 0. This is shown in FIG. Second layer 90 is deposited, for example, by conventional low pressure chemical vapor deposition techniques.

The thickness of second layer 90 ranges from about 1500 to about 2500 angstroms, with about 2000 angstroms being preferred. The specific thickness of layer 90, in combination with the specific thickness of layer 60, is approximately 2,500 't' (, to approximately 4,500 angstroms).
resulting in a composite thickness of The policy, recon layers 6o and 90 are I
The gate is about 2500 to about 450 to be later patterned to form a polysilicon gate of
It has a thickness in the range of 0 angstroms. Approximately 2500
Polysilicon thicknesses smaller than angstroms result in gates with undesirably high sheet resistance.
Undesirable. On the other hand, polysilicon thicknesses greater than about 4500 angstroms are undesirable because they result in very tall polysilicon gates and undesirably large sidewall capacitances.

Polycon 100 formed by deposition of two polysilicon layers 60 and 90 followed by a second polysilicon layer 90
is suitably doped with n or p dopants (using conventional techniques). Does the doping of polysilicon layers 60 and 90 (depending on whether the active layer 20 is of n-type or p-type conductivity) result in a highly conductive gate? (The polysilicon layer is patterned to form the gate.) The doping of the polysilicon 100 results in good electrical contact to the active layer 20. The dopants also extend throughout polycon 100 and into relatively highly doped regions 110. of active layer 20, as shown in FIG. , e.g. GOX
The source or train portion of the MOSFET is formed through which the polyconductor passes. Thereafter, the two polysilicon layers 60 and 90 are patterned using conventional techniques, and the fifth
MO3 in the GASAD region 50 as shown in the figure.
FET gate 120, selected 7't G A S A
A polysilicon runner 1 extends from the polysilicon gate 120 in the D region to the region layer below the other selected GASAD region to the polycon 100 extending through the GOX.
30 is formed.

The steps involved in completing a MO3IC are conventional. That is, (normal technique 1c J: 'p
) A self-lined source and a gate are formed on opposite sides of the gate, and an insulating layer such as a SiO□ layer is formed on opposite sides of the gate.
' is deposited on C. Conventional lithography techniques are used to cut windows in the insulating layer to expose the gate, source and train regions of the IC. Finally, a metal layer, for example copper-doped aluminum, is deposited on the IC (thus the metal is also deposited in the holes through the insulating layer, forming the metal electrodes to the gate, source and train regions). is patterned to form metal runners.

Synthetic metal silicide on polysilicon oxide For example, if tantalum silicide on polysilicon oxide is required, the soil fabrication process is modified so that the polysilicon layer is doped and then two polysilicon layers are climbed to form the metal silicide layer. be done. Both the silicide layer and the polysilicon layer are then patterned to form metal silicide on the polysilicon gates and metal silicide on the polysilicon runners extending from the selected gates to the polysilicon.

A very thin layer of SiO□, typically about IO angstroms, is formed on the surface of the first polysilicon layer 6o during the steps of the fabrication method of the present invention, prior to the deposition of the second polysilicon layer 9o. It should be noted that there is a tendency for

Thus, a polysilicon gate formed in accordance with the present invention includes two layers of polysilicon separated by a thin boundary layer of Sin, . This S Io
A thin boundary layer of 2 is detected in a transmission electron microscope (cross section) of an IC made according to the invention. However, this 51
The 02 layer is very thin (compared to the two layers of polysilicon) and the total amount of 81o2- is (compared to the total amount of polysilicon)
Because it is so small, 5102 has no appreciable negative effect on the conductance of polysilicon gates and polyconductors formed in accordance with the present invention.

EXAMPLES The method of the present invention can be applied to ring oscillators, line drivers,
It was used to fabricate VLSI MOS logic circuits including shift registers, 4-bit adders, and other devices. This VLSI MO8 logic circuit also includes a polycontainer,
Fabricated using 1 μm 11172 μm and 2 μm design rules.

The fabrication method of the present invention began by growing 8102 FOX approximately 3500 Angstroms thick on the surface of a 3 inch silicon wafer. This FOX was wet (
The silicon wafers were grown by total thermal oxidation in a H2O) atmosphere.

The active layer of the logic circuit is formed, and the dopant a degree at the silicon-FOX interface (this is the increasing shape rl/fO8 of the logic circuit)
These are the parameters that determine the threshold voltage of the FET gate. ), boron atoms were implanted into a silicon wafer coated with FOX at a dose of approximately 2 × 10 ”' cm −2 .
At about 170 KeV, boron atoms form silicon-FO
It was sufficient to reliably penetrate ILFOX"fr up to the X interface.

The G and A S A D on the surface of the wafer were exposed by opening a window in FOX using conventional phosphorography techniques. These windows (and GASAD regions) were approximately 7 μm long and 15 μm wide.

The wafer, approximately 250 angstroms thick and 5 in2
It was grown on the surface of each GASAD by heating at 0C for about 15 minutes. The wafer was then annealed at about 1000C GX for about 15 minutes in an argon atmosphere to reduce the fixed charge in the 5in2. This heat treatment also fully activates the boron implanted species. (Boron atoms replace silicon atoms in the silicon crystal lattice as a result of the argon anneal step.) A first layer of polysilicon approximately 1500 angstroms thick is then deposited using conventional low pressure chemical vapor deposition techniques. was deposited on the wafer using Next, an organic resist, commercially available from Philip A. Hunt Chemical, Le Corporation New Jersey, Paradise Park, under the trade name HPR-204 resist, was spin coded onto the wafer to a thickness of approximately 18 μm. It was baked at 210C for about 120 minutes. 5102 layers of gold approximately 1200 angstroms thick, plasma deposited on organic resist and approximately 35 layers of DCOPA (90% dichloro-propyl acrylate and 10% copolymer wood) X#J resist.
A thickness of 0.00 Å was spin-deposited onto a 1200 Å thick layer of Sin2.

After placing a polycon height mask over the GASAD area, the DCOPAX X-ray I nosyst was exposed to 4.37 angstrom X-ray radiation for approximately 5 minutes. The intensity of the radiation is approximately 7
It was 5μWatt/cm2. The X-ray resist was developed with a wet developer containing isopropyl alcohol and methyl ethyl ketone. Next, the patterned X
A 5 in 2 1200 angstrom thick gold pattern was formed by full wafer reactive sputter etching in CHF3 plasma using the line resist as an etch mask.

CHF3Ptesma flows CHF31 into the reaction vessel at a flow rate of about 79cc7min, maintains the pressure inside the reaction vessel about 10 mTorr1 (total power density 0,1 W)
It was formed by maintaining at 7 cm2.

Finally, the patterned X-ray resist layer and Si
Using the 02 layer as an etch mask, 0,,-CF
The HPR-204 resist was patterned by reactive sputter etching the wafer in a 1% CF''4 plasma.

This 02-CF plasma flows a mixture of 02 and CF4 (1% CF4) into the reaction vessel at a flow rate of about 83 Cc/min, the pressure inside the reaction vessel is 4 mTorr, and the power density is about 0. 2 Wa t t/cTn2.

Holes were then etched through the polysilicon layer by reactive sputter etching the polysilicon layer in a C12 plasma for approximately 5 minutes using the patterned resist as a full etch mask. (The holes were placed over the GASAD areas where polycon was required.) This etch occurred in a parallel plate, reactive sputter etcher and was approximately 2.
C12 scum flows into the reaction vessel at 0 cc/min, the total pressure in the reaction vessel is about 5 mTorr, and the power density is about 0.5 mTorr.
This was achieved by maintaining Wa t t /lv2. The polycon is then GOX-etched where desired by whole wafer reactive sputter etching in CHF'3 plasma (in a parallel plate reactive sputter etcher) using the patterned polysilicon layer as an etch mask.
'I penetrated and fucked the hole. During this final etching step, CHF3 was flowed into the reaction vessel at approximately 18 ccZ minutes;
The total pressure within the reaction vessel was maintained at approximately 68 millitorr and the power density was maintained at approximately 0.2 watts/c7n2.

Next, set the ambient temperature to about 8 CI? HPR-204°SiO□ and DCO'P are removed from the wafer surface by placing the wafer in a solution of sulfuric acid and hydrogen peroxide.
The AXil resist was completely removed.

The wafer surface was cleaned with common chemical solvents containing HF to remove resist residues.

A second layer of polysilicon approximately 2500 Angstroms thick was then deposited over the wafer surface using conventional low pressure chemical vapor deposition techniques. As a result, polysilicon was also deposited into the hole extending through the first polysilicon layer and GOX to the underlying silicon, forming polysilicon.

The two polysilicon layers and polycon are ordinary PBr3
The wafer was fully doped with phosphorus by placing it in a source furnace for about 60 minutes. The furnace temperature was maintained at approximately 950C. , this phosphorus diffusion process makes the polysilicon layer and polycon. type conduction (doping level was approximately 10"cm-3).

)Became. In addition, phosphorus is also pushed into the silicon region surrounding the polycondensate, and the MOS in which the polyconductor penetrates the GOX
The source or drain of the FET was partially formed.

The remaining steps in the fabrication of the VLSIMO3 logic circuit are:
It is a normal one, and the paper “Small + VR” by Watt et al.
o Electron beam for SFET, 19'81
It is published in November, Vol. ED-28, No. 11, page 1338.

[Brief explanation of the drawing]

1 to 5 are cross-sectional views of an electronic component (with a thin gate oxide) fabricated according to the invention at different fabrication steps. [Explanation of symbols of main parts] Semiconductor basics -m------20 Insulating layer -1-'--30 Mask layer -1--70 Protective layer ---=--60 Hole ----------80 Second conductive layer ---90 Conductor ---1--130 Electrode part -- -----------100

Claims (1)

[Claims] 1. A step of forming a thin insulating layer on a semiconductor substrate, a step of forming a mask layer on the insulating layer, a step of selectively etching the mask layer, and a step of etching the entire mask layer as a mask. In an integrated circuit manufacturing method comprising selectively etching the mask layer and removing the mask layer by a subsequent etching step, before forming the mask layer, a conductive protective layer is entirely formed on the thin layer to remove the protective layer. A method of manufacturing an integrated circuit, characterized in that the layer protects the thin layer during a mask layer removal process. 2. The method of claim 1, further characterized in that the thin insulating layer has a thickness of less than 400 angstroms. 3. The method according to claim 2, further characterized in that the thin insulating layer is SiO□ and the semiconductor substrate is silicon. 4. The method according to claim 3, further characterized in that the mask layer is a resist layer and is removed by chemical etching or plasma etching. 5. The method of manufacturing an integrated circuit according to claim 4, further characterized in that the protective layer is a polysilicon layer. 6. The method of claim 5, further characterized in that the polysilicon layer has a thickness in the range of about 1000 to about 2000 Angstroms. 7. The method according to claim 6, further characterized in that the protective layer of material is a layer of refractory metal. 8. In the method described in claim 7, the etching leg is performed so that a hole is formed through the protective layer and the insulating layer, and after the mask layer is removed, the second conductive layer is formed on the protective layer. A method of manufacturing an integrated circuit further comprising forming a second conductive layer through a hole to form a contact to a semiconductor body. 9. The method of claim 8, wherein the thin insulating layer is a gate oxide, and the conductive layer and the second conductive layer are etched to form a gate electrode on a portion of the gate oxide. A method of manufacturing integrated circuits characterized in that the conductor interconnects all contact parts of the gate electrode.