JPS6127898B2 - - Google Patents
Info
- Publication number
- JPS6127898B2 JPS6127898B2 JP49101668A JP10166874A JPS6127898B2 JP S6127898 B2 JPS6127898 B2 JP S6127898B2 JP 49101668 A JP49101668 A JP 49101668A JP 10166874 A JP10166874 A JP 10166874A JP S6127898 B2 JPS6127898 B2 JP S6127898B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- insulating film
- substrate
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 28
- 238000007747 plating Methods 0.000 description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 14
- 239000010931 gold Substances 0.000 description 14
- 229910052737 gold Inorganic materials 0.000 description 14
- 235000012239 silicon dioxide Nutrition 0.000 description 14
- 239000000377 silicon dioxide Substances 0.000 description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 12
- 239000010410 layer Substances 0.000 description 12
- 239000010936 titanium Substances 0.000 description 12
- 229910052719 titanium Inorganic materials 0.000 description 12
- 239000012212 insulator Substances 0.000 description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に半
導体装置のメツキ金属電極を形成する方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a plated metal electrode of a semiconductor device.
半導体装置において電極は極めて重要なもので
ありエレクトロマイグレーシヨンを防止し、高周
波特性や大電流特性を改善するためには電極を厚
くかつ均一に形成しなければならない。また半導
体装置の信頼度を向上させるために電極の少くと
も表面層を金で構成することが必要な場合が多
い。よく知られているように金は著るしく化学的
に安定な金属であるために、蒸着またはスパツタ
によつて得られる1ミクロン程度の比較的厚い膜
を写真蝕刻等の加工技術によつて半導体装置に要
求される数ミクロン程度の極微細な電極巾に精度
良く加工することは極めて困難である。このよう
な理由のため、通常はあらかじめ成形された下地
電極上に金をメツキすることによつて半導体装置
の金電極を形成している。このメツキの際にメツ
キ装置から被メツキ部分に電流を通じるための導
電材料を予め半導体装置の表面に形成しておかな
ければならない。このための導電材料としては、
金メツキ終了後容易に除去できるようにチタンま
たはクロム等が選ばれ、その形成は蒸着によつて
いる。しかるに半導体装置表面を覆う絶縁膜は電
極形成部ならびに半導体ウエハーを個々の半導体
装置に分割する際の分割部に相当する半導体装置
周縁部(すなわち、スクライブ領域)において予
め除去されておりこれら除去部で急激な段差を有
しているので、その上にメツキ用導電材料を蒸着
すると、絶縁膜の段差によつて導電材料の導電状
態が維持できなくなることが起り易いという欠点
がある。 Electrodes are extremely important in semiconductor devices, and in order to prevent electromigration and improve high frequency characteristics and large current characteristics, electrodes must be formed thick and uniformly. Furthermore, in order to improve the reliability of a semiconductor device, it is often necessary to make at least the surface layer of the electrode with gold. As is well known, gold is an extremely chemically stable metal, so a relatively thick film of about 1 micron, obtained by vapor deposition or sputtering, can be fabricated into a semiconductor using processing techniques such as photolithography. It is extremely difficult to precisely process electrodes to the ultra-fine electrode width of several microns required for the device. For this reason, gold electrodes of semiconductor devices are usually formed by plating gold on a pre-formed base electrode. During this plating, a conductive material must be previously formed on the surface of the semiconductor device in order to conduct current from the plating device to the portion to be plated. The conductive material for this purpose is
Titanium or chromium is selected so that it can be easily removed after gold plating, and its formation is by vapor deposition. However, the insulating film covering the surface of the semiconductor device is removed in advance at the electrode formation area and at the peripheral edge of the semiconductor device (i.e., the scribe area), which corresponds to the dividing area when dividing the semiconductor wafer into individual semiconductor devices. Since there is a sharp step difference, if a conductive material for plating is deposited on top of the step, there is a drawback that the conductive state of the conductive material is likely to be unable to be maintained due to the step difference in the insulating film.
この発明の目的は半導体装置の電極の少なくと
も一部をメツキによつて形成する場合に被メツキ
部分への電流通路とするための金属層が絶縁物の
段差部で電気的に断になることを防止する構造を
与え、厚くかつ均一にメツキ電極を形成すること
のできる半導体装置の製造方法を提供することに
ある。 An object of the present invention is to prevent electrical disconnection of the metal layer, which serves as a current path to the plated portion, at the stepped portion of the insulator when at least a portion of the electrode of a semiconductor device is formed by plating. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can provide a structure that prevents this problem and can form a thick and uniform plating electrode.
上記目的を達成するため本発明は、半導体基板
上に、この基板に選択的に形成された半導体領域
の一部を露出させるコンタクト穴および前記基板
のスクライブ領域を規定する周縁端部を有する第
1の絶縁膜を形成する工程と、前記コンタクト穴
よりも大きなコンタクト穴を有しかつ周縁端部が
前記第1の絶縁膜の周縁端部よりも内側に位置し
て前記第1の絶縁膜上に存在する第2の絶縁膜を
形成する工程と、前記第1および第2の絶縁膜を
有する前記基板の表面を導電膜で覆う工程と、前
記導電膜を電流パスとして前記半導体領域のため
のメツキ金属電極を選択的に形成する工程と、前
記メツキ金属電極をマスクにして前記導電膜を選
択除去する工程とを含むことを特徴とする。 To achieve the above object, the present invention provides a first semiconductor substrate having a contact hole exposing a part of a semiconductor region selectively formed in the substrate and a peripheral edge defining a scribe region of the substrate. forming an insulating film on the first insulating film having a contact hole larger than the contact hole and having a peripheral end located inside the peripheral end of the first insulating film; a step of forming an existing second insulating film, a step of covering the surface of the substrate having the first and second insulating films with a conductive film, and plating for the semiconductor region using the conductive film as a current path. The method is characterized in that it includes a step of selectively forming a metal electrode, and a step of selectively removing the conductive film using the plated metal electrode as a mask.
このように、本発明によれば、コンタクト穴お
よびスクライブ部分での絶縁膜端部の段差を緩和
している。よつて、表面全体に一様に機械的電気
的に安定な状態に導電膜を被着することが容易と
なる。この導電膜を被着後、導電膜を電流通路と
してメツキによつて電極形成部上の導電膜上に電
極を形成している。ここで上記の絶縁物の構成は
二酸化硅素等のみによる単層の場合と、二酸化硅
素等の絶縁膜上に前記二酸化硅素のナトリウムイ
オン等の汚染を防止するために、この膜上に更に
窒化硅素や酸化アルミニウム等の絶縁膜を重ねた
多層の場合があり、どちらの構成の場合も、絶縁
物端部の厚さを絶縁物内部から端部にかけて次第
に減少するように絶縁物端部を形成することによ
つて機械的電気的に安定な導電膜を被着させるこ
とができるものである。 As described above, according to the present invention, the step difference at the end of the insulating film at the contact hole and the scribe portion is alleviated. Therefore, it becomes easy to uniformly apply the conductive film to the entire surface in a mechanically and electrically stable state. After this conductive film is deposited, an electrode is formed on the conductive film on the electrode forming portion by plating, using the conductive film as a current path. Here, the structure of the above-mentioned insulator is a single layer made only of silicon dioxide, etc., and a case where silicon nitride is further added on the insulating film such as silicon dioxide to prevent contamination with sodium ions of the silicon dioxide. In some cases, it is a multilayer structure consisting of stacked insulating films such as aluminum oxide or aluminum oxide, and in both configurations, the insulator end is formed so that the thickness of the insulator end gradually decreases from the inside of the insulator to the end. This makes it possible to deposit mechanically and electrically stable electrically conductive films.
このように半導体装置の表面を被覆する絶縁物
をその除去部すなわち段差を生じる部分において
内部から端部にかけて次第に厚さを減少させるた
めに蒸着法によつてめつき電気通路となるための
導電膜が形成されたときに、この絶縁物段差が減
少させられているので、この部分で前記導電膜が
切断されるという不都合の発生は殆んど皆無とな
る。したがつてメツキによる半導体装置の電極形
成は極めて容易にできる。 In this way, in order to gradually reduce the thickness of the insulating material covering the surface of the semiconductor device from the inside to the end at the removed part, that is, the part where the step is created, a conductive film is plated using a vapor deposition method to form an electrical path. Since the insulator level difference is reduced when the conductive film is formed, there is almost no occurrence of the inconvenience that the conductive film is cut at this part. Therefore, electrodes of a semiconductor device can be formed extremely easily by plating.
次に本発明の好ましい実施例について図面を用
いてそれぞれ説明を加える。 Next, preferred embodiments of the present invention will be explained using the drawings.
第1図はこの発明の好ましい一実施例を示す。 FIG. 1 shows a preferred embodiment of the invention.
半導体基体11は任意の半導体領域12、例え
ばベース、エミツタ、ソース、ドレイン、アノー
ド、カソード等の必要な領域が全部形成された二
酸化硅素膜13で表面が被覆されている。この二
酸化硅素膜13を第1A図に示すように上記半導
体領域の電極形成部において、さらに上記装置の
周縁部において装置端部から20乃至30ミクロンの
巾で、写真蝕刻法によつてそれぞれ除去する。次
に上記二酸化硅素膜13を窒化硅素膜および二酸
化硅素膜で被覆し、最上層の二酸化硅素膜を電極
形成部において前記二酸化硅素膜13における開
孔よりも1ミクロン程度小さく、また上記装置の
周縁部において装置端部からの除去巾が二酸化硅
素膜13の端部に至るよりも2乃至3ミクロン短
かくなるように写真蝕刻法によつてそれぞれ除去
する。続いてこの最上層の二酸化硅素膜15をマ
スクとして、燐酸等で窒化硅素膜の電極形成部及
び装置周縁部を除去する。以上の工程によつて第
1B図に示す如く二酸化硅素膜13の表面を窒化
硅素膜14で包み込む形状で、絶縁物は全体とし
て周縁部及び電極形成部に面する端部においてそ
の厚さが絶縁物内部から端部にかけて次第に減少
するように形成される。次に第1C図に示すよう
に選択的に除去された絶縁物を有する半導体装置
表面全体にチタンを500A゜の厚さで蒸着する。
さらに第1D図に示すように前記チタン膜16の
電極形成部上に白金層17を蒸着によつて形成す
る。次に白金層17の上部表面のみを露出し、他
の表面をフオトレジスト膜19で被覆し、続いて
金メツキ浴中に半導体装置を浸し、別にメツキ浴
中に置いた金を陽極とし、チタン導電膜16を陰
極としてこのチタン導電膜16を電流通路として
メツキにより白金層17の上に金層18を形成す
ることにより電極を形成する。次に第1E図に示
すようにフオトレジスト膜19を除去した後熱硫
酸等により表面に露出している部分のチタン膜1
6を除去する。 The surface of the semiconductor substrate 11 is covered with a silicon dioxide film 13 in which all necessary semiconductor regions 12 such as a base, emitter, source, drain, anode, and cathode are formed. As shown in FIG. 1A, this silicon dioxide film 13 is removed by photolithography at the electrode forming portion of the semiconductor region and further at the periphery of the device in a width of 20 to 30 microns from the end of the device. . Next, the silicon dioxide film 13 is covered with a silicon nitride film and a silicon dioxide film. At each step, the removal width from the end of the device is 2 to 3 microns shorter than that reaching the end of the silicon dioxide film 13 by photolithography. Next, using the uppermost silicon dioxide film 15 as a mask, the electrode forming portion and the device peripheral portion of the silicon nitride film are removed using phosphoric acid or the like. Through the above steps, the surface of the silicon dioxide film 13 is wrapped in the silicon nitride film 14 as shown in FIG. It is formed so that it gradually decreases from the inside to the end. Next, as shown in FIG. 1C, titanium is deposited to a thickness of 500 .ANG. over the entire surface of the semiconductor device having the selectively removed insulator.
Furthermore, as shown in FIG. 1D, a platinum layer 17 is formed by vapor deposition on the electrode forming portion of the titanium film 16. Next, only the upper surface of the platinum layer 17 is exposed, and the other surface is covered with a photoresist film 19, and then the semiconductor device is immersed in a gold plating bath. An electrode is formed by forming a gold layer 18 on the platinum layer 17 by plating, using the conductive film 16 as a cathode and the titanium conductive film 16 as a current path. Next, as shown in FIG. 1E, after removing the photoresist film 19, the exposed portion of the titanium film 1 on the surface is treated with hot sulfuric acid or the like.
Remove 6.
最下層の二酸化硅素膜13、窒化硅素膜14お
よび最上層の二酸化硅素膜15が前記の周縁部の
スクライブ溝部および電極形成部の絶縁物端部で
全く同一周縁を共有するならば基体11表面から
最上層の二酸化硅素膜15の表面までの段差は極
めて大きなものとなり、この部分においてめつき
電流の通路となるべきチタン層16が電気的に接
続された状態を維持するためにはその蒸着膜厚は
この段差と同程度に厚くならなければならない。
さらにこのメツキ電流の通路となるべき部分のチ
タン層16は最終的には化学的に溶解除去される
が、メツキによつて形成された金属極18の下に
は残つていなければならない。しかしこの溶解除
去の際に金電極の下にある部分のチタンもそのほ
ぼ膜厚に等しい幅だけ細くなり、チタン膜厚と金
電極の幅が接近している場合は金電極下のチタン
幅が金電極幅に比して極めて細くなるかまたは残
存しなくなり半導体装置に対する有効な電極が形
成不可能となる。ところが本発明のように絶縁物
の厚さが絶縁物内部から端部にかけて次第に減少
する構造とすれば、チタン層16の厚さは充分薄
いままその導電層としての機能を果たすことが可
能となるので極めて微細な構造の金電極を容易に
実現することができる。 If the bottom layer silicon dioxide film 13, the silicon nitride film 14, and the top layer silicon dioxide film 15 share exactly the same periphery at the scribe groove portion of the periphery and the insulator end of the electrode forming portion, then from the surface of the base 11. The level difference to the surface of the uppermost silicon dioxide film 15 is extremely large, and in order to maintain the electrical connection of the titanium layer 16, which serves as a path for the plating current, the thickness of the deposited film is required. must be as thick as this step.
Further, the portion of the titanium layer 16 that is to become a path for the plating current is eventually chemically dissolved and removed, but must remain under the metal electrode 18 formed by plating. However, during this dissolution and removal, the titanium under the gold electrode also becomes thinner by a width approximately equal to its film thickness, and if the titanium film thickness and the width of the gold electrode are close, the width of the titanium under the gold electrode becomes The gold electrode becomes extremely thin compared to the width of the gold electrode or does not remain, making it impossible to form an effective electrode for a semiconductor device. However, if the thickness of the insulator is gradually reduced from the inside of the insulator to the ends as in the present invention, the titanium layer 16 can function as a conductive layer while remaining sufficiently thin. Therefore, gold electrodes with extremely fine structures can be easily realized.
第1図A乃至Eはこの発明の一実施例の各工程
を示す断面図である。
11は半導体基体、12は半導体領域、13お
よび15は二酸化硅素膜、14は窒化硅素膜、1
6はチタン膜、17は白金層、18は金電極、1
9はフオトレジスト膜である。
FIGS. 1A to 1E are cross-sectional views showing each step of an embodiment of the present invention. 11 is a semiconductor substrate, 12 is a semiconductor region, 13 and 15 are silicon dioxide films, 14 is a silicon nitride film, 1
6 is a titanium film, 17 is a platinum layer, 18 is a gold electrode, 1
9 is a photoresist film.
Claims (1)
れた半導体領域の一部を露出させるコンタクト穴
および前記基板のスクライブ領域を規定する周縁
端部を有する第1の絶縁膜を形成する工程と、前
記コンタクト穴よりも大きなコンタクト穴を有し
かつ周縁端部が前記第1の絶縁膜の周縁端部より
も内側に位置して前記第1の絶縁膜上に存在する
第2の絶縁膜を形成する工程と、前記第1および
第2の絶縁膜を有する前記基板の表面を導電膜で
覆う工程と、前記導電膜を電流パスとして前記半
導体領域のためのメツキ金属電極を選択的に形成
する工程と、前記メツキ金属電極をマスクにして
前記導電膜を選択除去する工程とを含むことを特
徴とする半導体装置の製造方法。1. Forming on a semiconductor substrate a first insulating film having a contact hole that exposes a part of a semiconductor region selectively formed on the substrate and a peripheral edge defining a scribe region of the substrate; forming a second insulating film having a contact hole larger than the contact hole and having a peripheral edge located inside the peripheral edge of the first insulating film and existing on the first insulating film; a step of covering the surface of the substrate having the first and second insulating films with a conductive film; and a step of selectively forming a plated metal electrode for the semiconductor region using the conductive film as a current path. and selectively removing the conductive film using the plated metal electrode as a mask.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10166874A JPS5128755A (en) | 1974-09-04 | 1974-09-04 | Handotaisochi no seizohoho |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10166874A JPS5128755A (en) | 1974-09-04 | 1974-09-04 | Handotaisochi no seizohoho |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18317882A Division JPS5878426A (en) | 1982-10-18 | 1982-10-18 | Preparation of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5128755A JPS5128755A (en) | 1976-03-11 |
JPS6127898B2 true JPS6127898B2 (en) | 1986-06-27 |
Family
ID=14306737
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10166874A Granted JPS5128755A (en) | 1974-09-04 | 1974-09-04 | Handotaisochi no seizohoho |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5128755A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS587671U (en) * | 1981-07-07 | 1983-01-18 | 株式会社松井色素化学工業所 | Transfer printing sheet |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4910673A (en) * | 1972-04-05 | 1974-01-30 | ||
JPS4915103A (en) * | 1972-06-02 | 1974-02-09 | ||
JPS4918577A (en) * | 1972-06-14 | 1974-02-19 | ||
JPS4933431A (en) * | 1972-07-26 | 1974-03-27 | ||
JPS4937578A (en) * | 1972-08-09 | 1974-04-08 |
-
1974
- 1974-09-04 JP JP10166874A patent/JPS5128755A/en active Granted
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4910673A (en) * | 1972-04-05 | 1974-01-30 | ||
JPS4915103A (en) * | 1972-06-02 | 1974-02-09 | ||
JPS4918577A (en) * | 1972-06-14 | 1974-02-19 | ||
JPS4933431A (en) * | 1972-07-26 | 1974-03-27 | ||
JPS4937578A (en) * | 1972-08-09 | 1974-04-08 |
Also Published As
Publication number | Publication date |
---|---|
JPS5128755A (en) | 1976-03-11 |
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