KR0148326B1 - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor device Download PDFInfo
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- KR0148326B1 KR0148326B1 KR1019950004451A KR19950004451A KR0148326B1 KR 0148326 B1 KR0148326 B1 KR 0148326B1 KR 1019950004451 A KR1019950004451 A KR 1019950004451A KR 19950004451 A KR19950004451 A KR 19950004451A KR 0148326 B1 KR0148326 B1 KR 0148326B1
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- insulating film
- insulating
- insulating layer
- etching
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 238000000206 photolithography Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000000463 material Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자 제조방법에 관한 것으로서, 특히 식각률이 산화막과 현저한 차이가 있는 절연막을 사용하여 작은 크기의 콘택 홀을 형성할 수 있는 반도체 소자 제조방법에 관한 것으로서, 실리콘 기판 상부에 제1절연막을 증착한 후 사진식각 공정으로 제1절연막의 일정 부분을 식각하는 단계, 상기 제1절연막보다 식각률이 높은 제2절연막을 전체 구조상부에 증착한 후 사진식각 공정에 의해 상기 제1절연막의 노출되는 끝단이 제2절연막의노출 부위에 위치하도록 제2절연막을 식각하는 단계, 상기 제2절연막보다 식각률이 높은 제3절연막을 전체 구조 상부에 증착 한 후 사진식각 공정으로 상기 제1절연막의 끝단과 제3절연막의 끝단이 일치하도록 제3절연막을 식각하여 콘택 홀을 형성하는 단계 및 소정의 금속 배선을 형성하는 단계로 이루어져서 현저한 식각률의 차이를 가지는 3가지의 절연막을 이용해서 비록 감광막의 노광에 의한 노출 부위가 크더라도 작은 폭의 콘택 홀을 형성할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a small contact hole can be formed using an insulating film having an etch rate significantly different from that of an oxide film. Etching and then etching a portion of the first insulating layer by a photolithography process, depositing a second insulating layer having a higher etching rate than the first insulating layer on the entire structure, and then exposing the first insulating layer by the photolithography process. Etching the second insulating film so as to be located at the exposed portion of the second insulating film, depositing a third insulating film having a higher etch rate than the second insulating film over the entire structure, and then using the photolithography process, the end of the first insulating film and the third insulating film are deposited. Etching the third insulating film so that the ends of the insulating film coincide with each other to form contact holes and forming predetermined metal wires; By using three insulating films having a significant difference in etch rate, a small contact hole can be formed even if the exposed portion of the photosensitive film is large.
Description
제1도 내지 제8도는 본 발명에 따른 반도체 소자 제조방법의 제조 공정을 나타내는 단면도.1 to 8 are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 제1절연막1 silicon substrate 2 first insulating film
3 : 제1감광막 4 : 제2절연막3: first photosensitive film 4: second insulating film
5 : 제2감광막 6 : 제3절연막5: second photosensitive film 6: third insulating film
7 : 제3감광막 8 : 콘택 홀7: third photosensitive film 8: contact hole
9 : 하부금속막 10 : 상부금속막9: lower metal film 10: upper metal film
본 발명은 반도체 소자 제조방법에 관한 것으로서, 특히 식각률이 산화막과 현저한 차이가 있는 절연막을 사용하여 작은 크기의 콘택 홀을 형성할 수 있는 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of forming a contact hole of a small size using an insulating film having an etch rate significantly different from that of an oxide film.
일반적으로 콘택(contact)이라 함은 반도체 기판과 금속 배선, 또는 금속 배선과 반도체 전극간의 전기적으로 연결함을 의미하며 대체적으로 콘택을 이루기 위해 하층의 금속 배선에 상층의 금속부와 전기적 절연을 목적으로 하는 절연층을 도포하고, 사진 식각 공정에 이한 콘택 홀을 형성하여 금속 또는 폴리실리콘을 콘택 홀의 오목부에 충진하여 콘택을 이루게 된다.In general, a contact means an electrical connection between a semiconductor substrate and a metal wiring, or a metal wiring and a semiconductor electrode, and is generally used for the purpose of electrically insulating the upper metal layer and the lower metal wiring to form a contact. The insulating layer is coated to form a contact hole following the photolithography process, and the metal or polysilicon is filled in the recess of the contact hole to form a contact.
그러나 최근 들어서 소자의 집적도가 증가함에 따라 상대적으로 콘택홀이 크기가 점점 미세화되는 추세인데 반해, 기존의 노광 기술로는 매우 작은 크기를 가지는 감광막 노출부위, 즉 콘택 홀의 형성이 불가능해서 새로운 콘택 홀 형성방법의 제시가 절실히 요구되었다.However, in recent years, as the degree of integration of devices increases, the size of contact holes becomes relatively smaller, whereas conventional exposure techniques make it impossible to form photoresist exposed portions, that is, contact holes, which have a very small size, thereby forming new contact holes. The presentation of the method was urgently needed.
이러한 요구에 부응한 본 발명은, 노광에 의한 감광막의 노출 부위가 커도 작은 크기의 콘택 홀의 형성이 가능한 반도체 소자 제조방법을 제공하는데 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming a contact hole of a small size even when the exposed portion of the photosensitive film by exposure is large.
상기와 같은 목적을 달성하기 위해 본 발명은, 실리콘 기판 상부에 제1절연막을 증착한 후 사진식각 공정으로 제1절연막의 일정 부분을 식각하는 단계, 상기 제1절연막보다 식각률이 높은 제2절연막을 전체 구조상부에 증착한 후 사진식각 공정에 의해 상기 제1절연막의 노출되는 끝단이 제2절연막의 노출 부위에 위치하도록 제2절연막을 식각하는 단계, 상기 제2절연막보다 식각률이 높은 제3절연막을 전체 구조 상부에 증착한 후 사진식각 공정으로 상기 제1절연막의 끝단과 제3절연막의 끝단이 일치하도록 제3절연막을 식각하여 콘택 홀을 형성하는 단계 및 소정의 금속 배선을 형성하는 단계로 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention, by depositing a first insulating film on the silicon substrate and etching a portion of the first insulating film by a photolithography process, the second insulating film having a higher etching rate than the first insulating film Etching the second insulating layer so that the exposed end of the first insulating layer is located at the exposed portion of the second insulating layer by depositing on the entire structure, and then etching the third insulating layer having a higher etch rate than the second insulating layer. Forming a contact hole by etching the third insulating layer so that the end of the first insulating layer and the end of the third insulating layer coincide with each other after the deposition on the entire structure. It features.
그리고 상기 금속 배선을 형성하는 단계는 전체 구조 상부에 하부금속막을 증착하고 상기 콘택 홀에만 상기 하부금속막이 남도록 상기 제2,3절연막 및 하부금속막을 제거한 후 상기 하부금속막 상부에 소정의 패턴으로 상부금속막을 형성하는 것이 바람직하다.The forming of the metal line may include depositing a lower metal layer on the entire structure, removing the second and third insulating layers and the lower metal layer so that the lower metal layer remains only in the contact hole, and then forming an upper portion in a predetermined pattern on the lower metal layer. It is preferable to form a metal film.
또한, 상기 제2,3절연막 및 하부금속막의 제거는 화학기계적 연마법을 사용하여 제거한다.In addition, the second and third insulating films and the lower metal film are removed using a chemical mechanical polishing method.
이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제1도 내지 제8도는 본 발명에 따른 반도체 소자 제조방법의 제조공정을 나타내는 단면도이다.1 to 8 are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the present invention.
제1도에 도시된 바와같이 실리콘 기판(1) 상부에 제1절연막(2)을 증착한 후, 제1감광막(3)을 도포하고 소정의 패턴으로 노광시켜 상기 제1절연막(2)의 일정 부위를 노출시킨다.As shown in FIG. 1, after the first insulating film 2 is deposited on the silicon substrate 1, the first photoresist film 3 is coated and exposed in a predetermined pattern so that the first insulating film 2 is uniformly formed. Expose the site.
그 다음, 제2도와 같이 상기 제1감광막 패턴(3)을 제거한 후, 전체구조 상부에 제2절연막(4)을 상기 제1절연막(2)의 두께보다 두껍게 형성하고, 상기 제2절연막(4)은 상기 제1절연막(2)의 식각률보다 큰 재질을 사용하여 이후에 실시될 건식식각시에 상기 제2절연막(4)만 식각되도록 한다. 그리고 전체 구조의 상부에 제2감광막(5)을 도포하고 소정의 패턴으로 노광시켜 상기 제2절연막(4)의 일정 부위를 노출시킨다. 이때, 상기 제2절연막(4)이 노출되는 폭은 상기 제1절연막(2)의 노출폭보다 크도록 형성한다. 즉, 상기 제2절연막(4)의 노출 부위에 상기 제1절연막(2)의 끝단이 포함되도록 한다.Next, after removing the first photoresist layer pattern 3 as shown in FIG. 2, the second insulation layer 4 is formed on the entire structure to be thicker than the thickness of the first insulation layer 2, and the second insulation layer 4 is formed. ) Is made of a material larger than the etching rate of the first insulating film 2 so that only the second insulating film 4 is etched during dry etching. Then, the second photosensitive film 5 is coated on the entire structure and exposed in a predetermined pattern to expose a predetermined portion of the second insulating film 4. In this case, the width of the second insulating film 4 is exposed to be larger than the exposure width of the first insulating film 2. That is, the end of the first insulating film 2 is included in the exposed portion of the second insulating film 4.
그 다음, 제3도와 같이 상기 제2절연막(4)의 노출 부위를 건식식각에 의해 상기 제2절연막(4)을 식각하는데, 여기서 상기 제1절연막(2)의 식각률이 상기 제2절연막(4)의 식각률보다 작기 때문에 상기 제1절연막(2)은 식각되지 않고 상기 제2절연막(4)만 식각되고, 또한 상기 제2절연막(4)의 노출 부위에 상기 제1절연막(2)의 끝단도 노출되게 된다. 그런 다음 상기 제2감광막 패턴(5)을 제거한다.Next, as illustrated in FIG. 3, the second insulating layer 4 is etched by dry etching the exposed portion of the second insulating layer 4, wherein the etch rate of the first insulating layer 2 is the second insulating layer 4. Since the first insulating film 2 is not etched, only the second insulating film 4 is etched, and the end of the first insulating film 2 is exposed to the exposed portion of the second insulating film 4. Exposed. Then, the second photoresist pattern 5 is removed.
그 다음, 제4도와 같이 전체 구조의 상부에 제3절연막(6)을 증착한후, 제3감광막(7)을 도포하고 소정의 패턴으로 노광시켜 상기 제3절연막(6)의 일정 부위가 노출되도록 한다. 여기서 상기 제3감광막 패턴(7)의 일측 끝단은 상기 제1절연막(2)의 끝단과 동일 수직선상에 일치되도록 형성한다. 또한, 상기 제3절연막(6)으로는 상기 제1,2절연막(2,4)의 식각률보다 큰 식각률을 가지는 재질을 사용하여 이후에 실시될 건식식각시 상기 제3절연막(6)만 식각되도록 한다.Next, as shown in FIG. 4, after depositing the third insulating film 6 on the entire structure, the third photosensitive film 7 is coated and exposed in a predetermined pattern to expose a predetermined portion of the third insulating film 6. Be sure to Here, one end of the third photoresist layer pattern 7 is formed to coincide with the end of the first insulating layer 2 on the same vertical line. In addition, the third insulating layer 6 may be formed of a material having an etching rate greater than that of the first and second insulating layers 2 and 4 so that only the third insulating layer 6 may be etched during dry etching. do.
그 다음, 제5도와 같이 상기 제3감광막 패턴(7)을 식각장벽층으로하여 상기 제3절연막(6)을 건식식각하여 콘택 홀(8)을 형성하여 상기 실리콘 기판(1)을 노출시키는데, 상기 제3절연막(6)의 식각률이 상기 제1,2절연막(2,4)의 식각률보다 높기 때문에 상기 제3절연막(6)만 식각되고 상기 제1,2절연막(2,4)은 식각되지 않고 그대로 남게 된다. 또한, 상기 콘택 홀(8)의 폭은 제2도에서 도시된 상기 제2감광막 패턴(5)의 노출폭보다 매우 작게 형성된다. 이후, 상기 제3감광막 패턴(7)을 제거한다.Next, as shown in FIG. 5, the third insulating layer 6 is dry-etched using the third photoresist pattern 7 as an etch barrier layer to form a contact hole 8 to expose the silicon substrate 1. Since the etching rate of the third insulating layer 6 is higher than that of the first and second insulating layers 2 and 4, only the third insulating layer 6 is etched and the first and second insulating layers 2 and 4 are not etched. It will remain. In addition, the width of the contact hole 8 is formed to be much smaller than the exposure width of the second photoresist pattern 5 shown in FIG. Thereafter, the third photoresist pattern 7 is removed.
그 다음, 제6도와 같이 상기 콘택 홀(8)에 하부금속막(9)을 CVD법에의해 선택적으로 완전매립되도록 형성한다. 즉, 상기 하부금속(9)의 높이를 상기 콘택 홀(8)의 높이와일치되도록 형성한다.Next, as shown in FIG. 6, the lower metal film 9 is formed in the contact hole 8 so as to be selectively completely filled by the CVD method. That is, the height of the lower metal 9 is formed to match the height of the contact hole 8.
그 다음, 제7도와 같이 상기 하부금속막(9)의 상부면보다 높게 형성된 상기 제2,3절연막(4,6)을 화학기계적 연마법으로 제거하여 평탄화를 이룬다.Next, as shown in FIG. 7, the second and third insulating films 4 and 6 formed higher than the upper surface of the lower metal film 9 are removed by chemical mechanical polishing to planarize the same.
마지막으로 제8도와 같이 상기 하부금속막(9)의 상부에 소정의 패턴으로 상부금속막(10)을 형성하여 반도체 소자가 완성된다.Finally, as shown in FIG. 8, the upper metal film 10 is formed on the lower metal film 9 in a predetermined pattern to complete the semiconductor device.
그리고 상기 제1,2,3절연막(2,4,6)은 식각률이 순차적으로 높은 재질을 사용하거나, 동일 재질이더라도 식각률의 현저한 차이를 가지도록 서로 다른 공정 조건에서 증착하여 형성해도 무방하다.The first, second, and third insulating films 2, 4, and 6 may be formed of materials having high etch rates sequentially or may be formed by depositing under different process conditions so as to have a significant difference in etch rates even if they are the same material.
이와같이 본 발명은 현저한 식각률의 차이를 가지는 3가지의 절연막을 이용해서 비록 감광막의 노광에 의한 노출 부위가 크게 형성되더라도 작은 폭의 콘택 홀을 형성할 수 있는 장점이 있다.As described above, the present invention has an advantage of forming a contact hole having a small width even though three exposed portions of the photoresist layer are formed by using three insulating layers having a significant difference in etching rate.
Claims (3)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950004451A KR0148326B1 (en) | 1995-03-04 | 1995-03-04 | Fabrication method of semiconductor device |
| US08/610,718 US5648298A (en) | 1995-03-04 | 1996-03-04 | Methods for forming a contact in a semiconductor device |
| CN96104049A CN1079578C (en) | 1995-03-04 | 1996-03-04 | Methods for forming contact in semiconductor device |
| TW085102620A TW295716B (en) | 1995-03-04 | 1996-03-04 | Methods for forming a contact in a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950004451A KR0148326B1 (en) | 1995-03-04 | 1995-03-04 | Fabrication method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960035801A KR960035801A (en) | 1996-10-28 |
| KR0148326B1 true KR0148326B1 (en) | 1998-12-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950004451A KR0148326B1 (en) | 1995-03-04 | 1995-03-04 | Fabrication method of semiconductor device |
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| Country | Link |
|---|---|
| KR (1) | KR0148326B1 (en) |
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| KR960035801A (en) | 1996-10-28 |
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