JPS61222171A - Power mos transistor - Google Patents
Power mos transistorInfo
- Publication number
- JPS61222171A JPS61222171A JP60047275A JP4727585A JPS61222171A JP S61222171 A JPS61222171 A JP S61222171A JP 60047275 A JP60047275 A JP 60047275A JP 4727585 A JP4727585 A JP 4727585A JP S61222171 A JPS61222171 A JP S61222171A
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- power mos
- grown
- diffused
- taken
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 3
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract description 4
- 239000000969 carrier Substances 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 2
- 230000003190 augmentative effect Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明はパワーＭＯ５）ランジスタに関するものである
。DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a power MO transistor.
〈発明の概要〉
シリコン（Ｓｉ）とゲルマニウム（Ｇｅ）とをエピタキ
シャル法でつみ重ねること等によって、ソース及びドレ
インをＳｉ１ゲ一ト対応部をＧｅの構造とする。<Summary of the Invention> By stacking silicon (Si) and germanium (Ge) together by an epitaxial method, etc., the source and drain are made to have a structure of Si1 and the corresponding part of the gate is made of Ge.
〈従来の技術〉
Ｎチャンネル及びＰチャンネルにせよ、従来のパワーＭ
Ｏ３）ランジスタはＳｉのみで構成されていた。これは
、Ｓｉの熱伝導性及びキャリアの移動度の良さによるも
のであった。<Prior art> Whether it is N channel or P channel, conventional power M
O3) The transistor was composed only of Si. This was due to the good thermal conductivity of Si and the good mobility of carriers.
１＜
第３図へ従来のＮチャンネルパワーＭＯ５）ランジスタ
の構成例を示す。Ｓはソース端子、Ｄはドレイン端子、
Ｇはゲート端子である。単一セルの平面図は第４図のと
おシである。ここにおいて、ソースｌ（表面のｎ＋層）
、ドレイン２（裏面のｎ＋層とＮ一層）、ゲート対応部
８（Ｐ層）は、すべてＳｉにより構成されている。1< Fig. 3 shows an example of the configuration of a conventional N-channel power MO5) transistor. S is the source terminal, D is the drain terminal,
G is a gate terminal. The plan view of the single cell is as shown in FIG. Here, source l (surface n+ layer)
, the drain 2 (the n+ layer and the N layer on the back surface), and the gate corresponding portion 8 (the P layer) are all made of Si.
〈発明が解決しようとする問題点〉
ところで、従来の構造はＳｉの物性常数等の制約から、
ある電流容量例えば１５Ａで、ＯＮ抵抗の低いパワーＭ
ＯＳトランジスタを作ろうとすると、チップサイズが大
きくなるとともに、通常クラスのゲート抵抗（ｒ（１）
では、ゲート容量が大きくなるため、応答スピードを余
り速くできなかった０
本発明は、かかる従来のパワーＭＯＳトランジスタの欠
点に鑑みてなされたもので、１つのウェハーからの取れ
数も多く、かつ良好な特性が得らハルパワーＭＯＳトラ
ンジスタを提供することを目的とする。<Problems to be solved by the invention> By the way, the conventional structure has problems due to constraints such as physical property constants of Si.
A power M with a certain current capacity, for example 15A, and low ON resistance.
When trying to make an OS transistor, the chip size increases and the gate resistance (r(1)
However, since the gate capacitance becomes large, the response speed cannot be made very fast.The present invention was made in view of the drawbacks of the conventional power MOS transistors, and it is possible to produce a large number of transistors from one wafer, and to achieve good results. The object of the present invention is to provide a hull power MOS transistor with excellent characteristics.
〈問題点を解決するための手段〉
、ゲート対応部を、誘電常数及びキャリアの移動度で優
れているＧｅによシ構成する。<Means for solving the problem> The gate corresponding portion is made of Ge which is excellent in dielectric constant and carrier mobility.
く作用〉 ば取れ数を飛躍的に増加できる。Effect〉 The number of breakouts can be dramatically increased.
〈実施例〉
第１図に本発明よりなるパワーＭＯ５）ランジスタの構
成例を示す。ソースｌ（表面のｎ＋）及びドレイン２（
裏面のｎ＋層とＮ一層）は、従来例と同様Ｓｉで構成さ
れているが、ゲート対応部８（Ｐ層）はＧｅにより構成
している。単一セルの平面図は第４図と同じである。<Embodiment> FIG. 1 shows an example of the configuration of a power MO transistor according to the present invention. Source l (surface n+) and drain 2 (
The n+ layer and the N layer on the back surface are made of Si as in the conventional example, but the gate corresponding portion 8 (P layer) is made of Ge. The plan view of the single cell is the same as in FIG.
パワーＭＯ５）ランジスタは、シュミレーションによれ
ば誘電常数の大きい方がよく、５ｉ＝１２ε６．Ｇｅ＝
１６ε０
（ε０＝真空の誘電常数）
で、電流容量（ソース・ドレイン間電流ＩＤ５）はこの
値に平方根的に比例する。すなわち、本例の構造によれ
ば、ゲート対応部３をＧｅとしているので、電流容量は
従来の
倍となる。According to simulation, it is better for the power MO5) transistor to have a larger dielectric constant, 5i=12ε6. Ge=
16ε0 (ε0=vacuum dielectric constant), and the current capacity (source-drain current ID5) is square root proportional to this value. That is, according to the structure of this example, since the gate corresponding portion 3 is made of Ge, the current capacity is twice that of the conventional one.
さらに、パワーＭＯ５）ラッジスタはキャリアの移動度
が大きい程よい。Ｎチャンネルで考えると、常温付近で
は、
Ｓ ｉ （μｎ）＝４．ＯＸ １０’ｘＴ″″′Ｌ５ｃ
ｄ／Ｖ＠５ｅｃＧｅ（μｎ）＝４．９６Ｘ１０ ｘＴｃ
ｄ／Ｖ１１Ｓｅｃ（Ｔ：絶対温度）
となる。具体的な値で言えば、
単位：ｄ／Ｖ＠Ｓｅｃ
であり、約１．４９〜１．７９倍である。Furthermore, the higher the mobility of the carriers, the better the power MO5) radial star. Considering the N channel, near room temperature, S i (μn) = 4. OX 10'xT'''''L5c
d/V@5ecGe(μn)=4.96X10xTc
d/V11Sec (T: absolute temperature). In terms of specific values, unit: d/V@Sec, which is approximately 1.49 to 1.79 times.
電流容量全体では、誘電常数分と移動変分の和で表わさ
れ得るので、本例構造による電流容量は従来の２倍弱〜
２倍強となる。Since the entire current capacity can be expressed as the sum of the dielectric constant and the moving variation, the current capacity with this structure is slightly less than twice that of the conventional structure.
That's more than double.
逆に必要電流容量を同一値とすると、ソースの周辺Ｗ（
第４図ソース（（Ｓ））電極参照）との関係において、
本例構造による°パワーＭＯＳ）ランジスタでは、従来
のＷを１／２にできることとなる。すなわち、Ｗの一辺
の長さをｒとすると、その面積Ｓは５＝ｒ２であり、ｒ
を１／２にできるということはセルサイズを（１／２）
＝１／４にできる。Conversely, if the required current capacity is the same value, the surrounding W of the source (
In relation to the source (see (S) electrode) in Figure 4,
In the power MOS transistor having the structure of this example, W can be halved compared to the conventional one. That is, if the length of one side of W is r, its area S is 5=r2, and r
can be reduced to 1/2, which means that the cell size can be reduced to (1/2)
= 1/4.
つまり、本例構造によれば、チップサイズは１／４で、
従来並みの特性が得られる。取れ数で言えば４倍である
。In other words, according to the structure of this example, the chip size is 1/4,
Characteristics comparable to conventional ones can be obtained. In terms of the number of wins, it is four times as many.
さらにチップサイズがｌ／４になると格子欠陥に入る確
率も１／４となる。歩留りも考慮すると、４２〜１６倍
の生産性をもつことになる。仮に、スペースファクタが
あるとしても、実質的取れ数は少なくとも１０倍以上が
得られる可能性がある。Furthermore, when the chip size becomes 1/4, the probability of a lattice defect occurring also becomes 1/4. If the yield is also considered, the productivity will be 42 to 16 times higher. Even if there is a space factor, there is a possibility that the actual yield will be at least 10 times greater.
第２図に本発明によるパワーＭＯ８）ランジスタのプロ
セス例を示しておく。Ｎ型のＳｉウエノ為−を用い（第
１工程）、この上にＭＯＣＶＤ法によりＧｅを成長させ
る（第２工程）。次にこれにＰ型不純物を拡散させる（
第３工程）。さらに再びＭＯＣＶＤ法により今度はＳｉ
を成長させ、Ｎ型不純物を拡散させる（第４工程）。こ
れを断面Ｖ字状にメサ・エツチングしく第５工程）、ソ
ース端子、ドレイン端子り、ゲート端子Ｇの電極付けを
行なう（第６エ程）Ｏ
５ｉとＧｅ の親和性を比較すると、次のとおりであ
り、劣化の心配はない０
以上実施例ではＮチャンネルパワーＭＯ５）ランジスタ
で説明したが、ＰチャンネルパワーＭＯＳトランジスタ
も同様に構成できることは明らかである。また、プロセ
スも第２図のもの限られることなく種々の適当な方法が
可能である。FIG. 2 shows a process example of a power MO8) transistor according to the present invention. An N-type Si substrate is used (first step), and Ge is grown thereon by MOCVD (second step). Next, diffuse P-type impurities into this (
3rd step). Furthermore, by the MOCVD method again, this time Si
is grown and an N-type impurity is diffused (fourth step). This is mesa-etched into a V-shaped cross section (5th step), and the source terminal, drain terminal, and gate terminal G are attached (6th step). Comparing the affinities of O 5i and Ge, we find the following: This is true, and there is no risk of deterioration. In the above embodiments, the N-channel power MOS transistor was explained, but it is clear that a P-channel power MOS transistor can be constructed in the same way. Further, the process is not limited to that shown in FIG. 2, and various suitable methods are possible.
〈発明の効果〉
以上のように本発明によれば、取れ数も多く、かつ良好
な特性を有する有用なパワーＭＯ５）ランジスタが提供
できる。<Effects of the Invention> As described above, according to the present invention, it is possible to provide a useful power MO transistor with a large number of parts and good characteristics.
第１図は本発明の一実施例を示す断面構成図、第２図は
プロセス例を示す工程図、第３図は従来例を示す断面構
成図、第４図は単一セルの平面図である。
１・・・ソース、２・・・ドレイン、３・・・ゲート対
応部。
代理人 弁理士 福 士 愛 彦（他２名）８１
＃−
Ｄ Ｉｆ） 第４図
第３ｒｆｉＪFig. 1 is a cross-sectional configuration diagram showing an embodiment of the present invention, Fig. 2 is a process diagram showing a process example, Fig. 3 is a cross-sectional configuration diagram showing a conventional example, and Fig. 4 is a plan view of a single cell. be. 1... Source, 2... Drain, 3... Gate corresponding part. Agent Patent attorney Aihiko Fukushi (and 2 others) 81
#- D If) Fig. 4 3 rfiJ
Claims (1)
し、ゲート対応部をゲルマニウム（Ｇｅ）により構成し
たことを特徴とするパワーＭＯＳトランジスタ。1. A power MOS transistor characterized in that the source and drain are made of silicon (Si), and the gate corresponding part is made of germanium (Ge).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60047275A JPS61222171A (en) | 1985-03-07 | 1985-03-07 | Power mos transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60047275A JPS61222171A (en) | 1985-03-07 | 1985-03-07 | Power mos transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61222171A true JPS61222171A (en) | 1986-10-02 |
Family
ID=12770736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60047275A Pending JPS61222171A (en) | 1985-03-07 | 1985-03-07 | Power mos transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61222171A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6393144A (en) * | 1986-05-19 | 1988-04-23 | テキサス インスツルメンツ インコ−ポレイテツド | Transistor construction of epitaxial system layers and manufacture of the same |
| JPH01196874A (en) * | 1988-02-02 | 1989-08-08 | Nippon Denso Co Ltd | Insulated-gate semiconductor device |
| JPH06224435A (en) * | 1992-12-02 | 1994-08-12 | Internatl Business Mach Corp <Ibm> | Metal oxide semiconductor heterojunction field-effect transistor (moshfet) |
-
1985
- 1985-03-07 JP JP60047275A patent/JPS61222171A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6393144A (en) * | 1986-05-19 | 1988-04-23 | テキサス インスツルメンツ インコ−ポレイテツド | Transistor construction of epitaxial system layers and manufacture of the same |
| JPH01196874A (en) * | 1988-02-02 | 1989-08-08 | Nippon Denso Co Ltd | Insulated-gate semiconductor device |
| JPH06224435A (en) * | 1992-12-02 | 1994-08-12 | Internatl Business Mach Corp <Ibm> | Metal oxide semiconductor heterojunction field-effect transistor (moshfet) |
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