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JPH05283617A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH05283617A
JPH05283617A JP7710692A JP7710692A JPH05283617A JP H05283617 A JPH05283617 A JP H05283617A JP 7710692 A JP7710692 A JP 7710692A JP 7710692 A JP7710692 A JP 7710692A JP H05283617 A JPH05283617 A JP H05283617A
Authority
JP
Japan
Prior art keywords
layer
output transistor
type
substrate
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7710692A
Other languages
Japanese (ja)
Inventor
Hirokazu Kawagoe
弘和 河越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP7710692A priority Critical patent/JPH05283617A/en
Publication of JPH05283617A publication Critical patent/JPH05283617A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To simplify the structure by allowing a transistor for output and a circuit for controlling and protecting it to be formed at a time of buried layer formation and epitaxial layer growth on the same semiconductor substrate while requiring no formation of a separation layer and being able to shorten a process. CONSTITUTION:After providing an N-type buried layer 4a on a region to form a transistor 15 for output, a P-type epitaxial layer 3 of a reverse conducting type to a substrate 1 is made to grow on an N<+> semiconductor substrate and a transistor for output is formed on a region where the N-type diffusion layers 5a, 5b of the same conductivity type as the substrate 1 are formed so as to contact with the buried layer 4a from the surface of the P-type epitaxial layer 3, a circuit 16 control-protecting the transistor 15 for output is formed on the P-type epitaxial layer 3 excepting the part where the transistor 15 for output is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は出力用トランジスタを制
御・保護する回路を設けた半導体装置およびその製造方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit for controlling and protecting an output transistor and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来この種の半導体装置およびその製造
方法は、図4に示すように、N+ 型サブ1上N型埋込層
4bを出力用トランジスタを形成する領域15に設け、
P型エピタキシャル3を成長させたのち、出力用トラン
ジスタと回路を形成する領域に分けN型埋込層4a,4
aを設け、P型分離層2を出力用トランジスタと回路の
間に設けたのち、N型エピタキシャル14をを成長さ
せ、N型埋込層4aと4bが接触するようにし、N型エ
ピタキシャル表面に出力用トランジスタ15と制御・保
護回路16を形成していた。
2. Description of the Related Art Conventionally, in this type of semiconductor device and its manufacturing method, as shown in FIG. 4, an N + buried layer 4b on an N + type sub 1 is provided in a region 15 for forming an output transistor,
After growing the P-type epitaxial layer 3, it is divided into regions for forming an output transistor and a circuit, and N-type buried layers 4a, 4
a is provided, the P-type isolation layer 2 is provided between the output transistor and the circuit, and then the N-type epitaxial layer 14 is grown so that the N-type buried layers 4a and 4b come into contact with each other. The output transistor 15 and the control / protection circuit 16 are formed.

【0003】[0003]

【発明が解決しようとする課題】ところで、上記従来の
半導体装置およびその製造方法は、縦型出力用トランジ
スタとそれを制御・保護する回路を電気的に分離して同
一半導体基板上に形成するための基板作成に、2回のエ
ピタキシャル成長と、2回の埋込層形成と分離層形成が
必要であり、工程が複雑であった。
By the way, in the conventional semiconductor device and the manufacturing method thereof, the vertical output transistor and the circuit for controlling / protecting it are electrically separated and formed on the same semiconductor substrate. In order to prepare the substrate, it was necessary to perform the epitaxial growth twice, the buried layer formation and the separation layer formation twice, and the process was complicated.

【0004】[0004]

【課題を解決するための手段】上記の問題を解決するた
めに、本発明は半導体基板上に出力用トランジスタとそ
の出力用トランジスタを制御・保護する回路を有する半
導体装置上において、半導体基板上に基板と同一導電型
の不純物埋込層を出力用トランジスタを形成する領域に
設け、その上に形成した基板と逆導電型層表面から基板
と同一導電型の拡散層を前記埋込層と接触するように形
成した領域に出力用トランジスタを形成し、前記回路を
出力用トランジスタを形成した以外の領域に形成した構
成を有する。
In order to solve the above-mentioned problems, the present invention provides a semiconductor device having an output transistor and a circuit for controlling and protecting the output transistor on a semiconductor substrate. An impurity buried layer of the same conductivity type as the substrate is provided in a region where the output transistor is formed, and a diffusion layer of the same conductivity type as the substrate is brought into contact with the buried layer from the surface of the opposite conductivity type layer of the substrate formed thereon. An output transistor is formed in the region thus formed, and the circuit is formed in a region other than the region where the output transistor is formed.

【0005】その製法は、一導電型半導体基板表面の出
力用トランジスタ形成部に一導電型の埋込層を形成する
工程と、その表面に他導電型の層をエピタキシャル成長
する工程と、その表面の出力用トランジスタ形成部に一
導電型の拡散層を前記埋込層に接続するよう形成する工
程と、前記拡散層の形成と同時ももしくは別工程で前記
出力用トランジスタ形成部でない表面に一導電型の他の
拡散層を形成する工程と、前記拡散層内に基板を電極と
する出力用トランジスタを形成する工程と、前記他の拡
散層内および、または外に回路素子を形成する工程とを
有すること特徴とする。
The manufacturing method is as follows: a step of forming a buried layer of one conductivity type in an output transistor formation portion on the surface of a semiconductor substrate of one conductivity type; a step of epitaxially growing a layer of another conductivity type on the surface; A step of forming a diffusion layer of one conductivity type in the output transistor forming portion so as to connect to the buried layer, and a step of forming one diffusion layer on the surface other than the output transistor forming portion at the same time as or in a step of forming the diffusion layer. Other diffusion layer, a step of forming an output transistor having a substrate as an electrode in the diffusion layer, and a step of forming a circuit element in and / or outside the other diffusion layer. It is characterized.

【0006】[0006]

【作用】上記の構成によると出力用トランジスタとそれ
を制御・保護する回路を同一半導体基板上に電気的に分
離し形成するため上1回に埋込層形成と、1回のエピタ
キシャル成長で形成でき工程が短く構造が簡単になる。
According to the above structure, the output transistor and the circuit for controlling and protecting the output transistor are electrically separated and formed on the same semiconductor substrate, so that the buried layer can be formed once and the epitaxial growth can be performed once. The process is short and the structure is simple.

【0007】[0007]

【実施例】以下、この発明について図面を参照して説明
する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

【0008】図1は本発明の一実施例を示す縦断面図で
あり、図2は図1の等価回路図である。図において、1
はN+ 型サブ,3はP型エピタキシャル層,4aはN型
埋込層,5a,5bはN型拡散層,6はN+ 拡散層,7
はP+ 拡散層,8はゲート,9は配線,10はGND,
11はP型ベース層,15は出力用トランジスタ,16
は制御・保護回路,17は出力用トランジスタ,18は
Pチャンネルトランジスタ,19はNチャンネルトラン
ジスタである。
FIG. 1 is a longitudinal sectional view showing an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of FIG. In the figure, 1
Is an N + type sub layer, 3 is a P type epitaxial layer, 4a is an N type buried layer, 5a and 5b are N type diffusion layers, 6 is an N + diffusion layer, 7
Is a P + diffusion layer, 8 is a gate, 9 is a wiring, 10 is GND,
11 is a P-type base layer, 15 is an output transistor, 16
Is a control / protection circuit, 17 is an output transistor, 18 is a P-channel transistor, and 19 is an N-channel transistor.

【0009】次に、上記の半導体装置の製造方法につい
て説明する。N型サブ1にN型不純物埋込層4aを形成
したのち、P型エピタキシャル3を成長させる。P型エ
ピタキシャル3表面より出力用トランジスタとPチャン
ネルトランジスタを形成する領域にN型拡散層5a,5
bを形成し、そのN型拡散層5aはN型不純物埋込層4
aと接触するように形成する。この実施例によれば、縦
型出力用トランジスタとそれを制御・保護する回路と
を、1回の埋込層形成と、1回のエピタキシャル成長に
より電気的に分離し形成することができる。
Next, a method of manufacturing the above semiconductor device will be described. After the N type impurity buried layer 4a is formed in the N type sub 1, the P type epitaxial layer 3 is grown. N-type diffusion layers 5a, 5 are formed in the region where the output transistor and the P-channel transistor are formed from the surface of the P-type epitaxial layer 3.
b, and the N-type diffusion layer 5a is formed into the N-type impurity buried layer 4
It is formed so as to contact with a. According to this embodiment, the vertical output transistor and the circuit for controlling and protecting the same can be electrically separated and formed by one buried layer formation and one epitaxial growth.

【0010】[0010]

【実施例2】図2は、この発明の第2の実施例の縦断面
図である。この実施例は前記第1の実施例の不純物をす
べて逆導電型とし、出力用トランジスタをPチャンネル
にしたこと以外第1の実施例と同様であるため、同一部
分には同一参照符号を付して説明を省略する。
[Embodiment 2] FIG. 2 is a vertical sectional view of a second embodiment of the present invention. This embodiment is the same as the first embodiment except that the impurities of the first embodiment are all of the opposite conductivity type and the output transistor is a P-channel, so the same parts are designated by the same reference numerals. And the description is omitted.

【0011】この実施例において、製造方法,作用効果
とも第1の実施例と同様となる。
In this embodiment, the manufacturing method and the working effects are the same as those in the first embodiment.

【0012】[0012]

【発明の効果】以上説明したように、この発明は、半導
体基板上に出力用トランジスタとその出力用トランジス
タを制御・保護する回路を有する半導体装置において、
半導体基板上に基板と同一導電型の不純物埋込層を出力
用トランジスタを形成する領域に設けたのち基板と逆導
電型のエピタキシャル層を成長させ、前記エピタキシャ
ル層表面から基板と同一導電型の拡散層を前記埋込層と
接触するように形成した領域に出力用トランジスタを形
成し前記回路を出力用トランジスタを形成した以外のエ
ピタキシャル領域に形成したことにより、縦型出力用ト
ランジスタと、それを制御・保護する回路が1回の埋込
層形成と1回のエピタキシャル層成長で同一半導体基板
上に形成することができ、分離層形成が必要なく工程が
短縮でき、構造が簡単になるという効果がある。
As described above, the present invention provides a semiconductor device having an output transistor and a circuit for controlling / protecting the output transistor on a semiconductor substrate.
An impurity buried layer of the same conductivity type as that of the substrate is provided on the semiconductor substrate in the region where the output transistor is formed, and then an epitaxial layer of the conductivity type opposite to that of the substrate is grown, and diffusion of the same conductivity type as the substrate is performed from the surface of the epitaxial layer. A vertical output transistor and controlling it by forming an output transistor in a region formed in contact with the buried layer and forming the circuit in an epitaxial region other than the formation of the output transistor. -The circuit to be protected can be formed on the same semiconductor substrate by one-time buried layer formation and one-time epitaxial layer growth, and it is possible to shorten the process without forming a separation layer and simplify the structure. is there.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の一実施例の縦断面図FIG. 1 is a vertical sectional view of an embodiment of the present invention.

【図2】 本発明の一実施例の等価回路FIG. 2 is an equivalent circuit of an embodiment of the present invention.

【図3】 本発明の第2の実施例の縦断面図FIG. 3 is a vertical sectional view of a second embodiment of the present invention.

【図4】 従来技術の縦断面図FIG. 4 is a vertical sectional view of a conventional technique.

【符号の説明】[Explanation of symbols]

1 N型サブ 3 P型エピタキシャル層 4a,4b N型埋込層 5a,5b N型拡散層 6 N+ 拡散層 7 P+ 拡散層 8 ゲート 9 配線 10 GND 12 配線 13 P型拡散層 14 N型エピタキシャル層 15 出力用トランジスタ 16 制御・保護回路 17 出力用トランジスタ等価回路 18 Pチャンネルトランジスタ 19 Nチャンネルトランジスタ 20 P型サブ 21 N型エピタキシャル層 23 P型拡散層 24 N型ベース層 25 出力用トランジスタ1 N-type sub 3 P-type epitaxial layer 4a, 4b N-type buried layer 5a, 5b N-type diffusion layer 6 N + diffusion layer 7 P + diffusion layer 8 Gate 9 wiring 10 GND 12 wiring 13 P-type diffusion layer 14 N type Epitaxial layer 15 Output transistor 16 Control / protection circuit 17 Output transistor equivalent circuit 18 P-channel transistor 19 N-channel transistor 20 P-type sub 21 N-type epitaxial layer 23 P-type diffusion layer 24 N-type base layer 25 Output transistor

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に出力用トランジスタとその
出力用トランジスタを制御・保護する回路を有する半導
体装置において、 半導体基板上に基板と同一導電型の不純物埋込層を出力
用トランジスタを形成する領域に設け、その上に形成し
た基板と逆導電型の層表面から基板と同一導電型の拡散
層を前記埋込層と接触するように形成した領域に出力用
トランジスタを形成し、前記回路を出力用トランジスタ
を形成した以外の基板と逆導電型の層に形成したことを
特徴とする半導体装置。
1. A semiconductor device having an output transistor and a circuit for controlling and protecting the output transistor on a semiconductor substrate, wherein an impurity-embedded layer having the same conductivity type as the substrate is formed on the semiconductor substrate. An output transistor is formed in a region formed in a region where a diffusion layer of the same conductivity type as that of the substrate is formed so as to be in contact with the embedded layer from the surface of a layer of a conductivity type opposite to that of the substrate formed on the region, and the above circuit is formed. A semiconductor device characterized by being formed on a layer of a conductivity type opposite to that of a substrate other than the substrate on which the output transistor is formed.
【請求項2】一導電型半導体基板表面の出力用トランジ
スタ形成部に一導電型の埋込層を形成する工程と、 その表面に他導電型の層をエピタキル成長する工程と、 そのエピタキシャル層表面の出力用トランジスタ形成部
に一導電型の拡散層を前記埋込層に接続するよう形成す
る工程と、 前記拡散層の形成と同時にもしくは別工程で前記出力用
トランジスタ形成部でない表面に一導電型の他の拡散層
を形成する工程と、 前記拡散層内に基板を電極とする(縦型)出力用トラン
ジスタを形成する工程と、 前記他の拡散層内および(または)外に回路素子を形成
する工程とを有することを特徴とする半導体装置の製造
方法。
2. A step of forming a buried layer of one conductivity type in an output transistor forming portion on the surface of a semiconductor substrate of one conductivity type, a step of epitaxially growing a layer of another conductivity type on the surface, and a surface of an epitaxial layer thereof. Forming a diffusion layer of one conductivity type in the output transistor forming portion so as to be connected to the buried layer; and forming one diffusion layer on the surface other than the output transistor forming portion at the same time as the formation of the diffusion layer or in another step. Another diffusion layer, a step of forming a (vertical) output transistor using the substrate as an electrode in the diffusion layer, and a circuit element inside and / or outside the other diffusion layer. A method of manufacturing a semiconductor device, comprising:
JP7710692A 1992-03-31 1992-03-31 Semiconductor device and manufacture thereof Pending JPH05283617A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7710692A JPH05283617A (en) 1992-03-31 1992-03-31 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7710692A JPH05283617A (en) 1992-03-31 1992-03-31 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH05283617A true JPH05283617A (en) 1993-10-29

Family

ID=13624533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7710692A Pending JPH05283617A (en) 1992-03-31 1992-03-31 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH05283617A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798538A (en) * 1995-11-17 1998-08-25 International Rectifier Corporation IGBT with integrated control

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798538A (en) * 1995-11-17 1998-08-25 International Rectifier Corporation IGBT with integrated control

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