JPS61170079A - Semiconductor light-receiving element - Google Patents
Semiconductor light-receiving elementInfo
- Publication number
- JPS61170079A JPS61170079A JP60010471A JP1047185A JPS61170079A JP S61170079 A JPS61170079 A JP S61170079A JP 60010471 A JP60010471 A JP 60010471A JP 1047185 A JP1047185 A JP 1047185A JP S61170079 A JPS61170079 A JP S61170079A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- avalanche multiplication
- region
- light absorption
- carrier concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- 239000000969 carrier Substances 0.000 claims abstract description 12
- 230000031700 light absorption Effects 0.000 claims description 42
- 230000005684 electric field Effects 0.000 abstract description 22
- 230000003287 optical effect Effects 0.000 abstract description 7
- 238000010521 absorption reaction Methods 0.000 abstract description 5
- 238000002347 injection Methods 0.000 abstract description 3
- 239000007924 injection Substances 0.000 abstract description 3
- 230000035945 sensitivity Effects 0.000 abstract description 3
- 238000005192 partition Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 88
- 238000000098 azimuthal photoelectron diffraction Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 239000011247 coating layer Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
- H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
（発明の技術分野）
本発明は、入射光を吸収してキャリアを発生する光吸収
領域と発生したキャリアを増倍するなだれ増倍領域とが
分離して形成された半導体受光素子に関する。Detailed Description of the Invention (Technical Field of the Invention) The present invention is characterized in that a light absorption region that absorbs incident light and generates carriers and an avalanche multiplication region that multiplies the generated carriers are formed separately. This invention relates to a semiconductor light receiving element.
〔発明の技術的背景とその問題点）
波長１．０〜１．６μｍ帯の半導体受光素子として、雑
音・暗電流特性の劣るＧｅを用いたアバランシェ・ホト
・ダイオード（ＡＰＤ）に代わり、Ｉ ｎＧａＡｓを用
いたＡＰＤが注目されている。[Technical background of the invention and its problems] As a semiconductor light-receiving element in the wavelength band of 1.0 to 1.6 μm, InGaAs is used instead of an avalanche photodiode (APD) using Ge, which has poor noise and dark current characteristics. APD using
ところが禁制帯幅の狭いＩｎＧａＡＳは、高電界をかけ
るとなだれ増倍によるアバランシェ降伏よりもトンネル
効果によるツェナー降伏を起こし易く、これだけでは低
暗電流の良好な特性をもつＡＰＤを実現することができ
ない。この欠点を解決するため、光吸収はＩ ｎＧａＡ
ｓ層で行ない、なだれ増倍は禁制帯幅の広い１ｎＰやＡ
ａＩｎＡＳ層で行なうようにした光吸収領域となだれ増
倍領域分離型のＡＰＤ （ＡＰＤ ｗｉｔｈ ５ｅｐ
ａｒａｔｅｄ ａｂｓｏｒａｔｉｏｎ ａｎｄ １ｕｌ
ｔｉｐｌｉｃａｔｉｏｎ ｒｅｏｉｏｎｓ 、以下Ｓ
ＡＭ−ＡＰＤと略称）が提案されている。However, when a high electric field is applied to InGaAS, which has a narrow forbidden band width, Zener breakdown due to tunneling effect is more likely to occur than avalanche breakdown due to avalanche multiplication, and this alone cannot realize an APD with good characteristics of low dark current. To overcome this drawback, the light absorption is InGaA
It is carried out in the s layer, and avalanche multiplication is performed using 1nP and A, which have a wide forbidden band.
APD with separated light absorption region and avalanche multiplication region using an aInAS layer (APD with 5ep
arated absorption and 1ul
tiplication reoions, hereafter S
AM-APD) has been proposed.
しかしながらこのＳＡＭ−ＡＰＤにおいても未だ解決す
べき問題がある。即ち、逆バイアス電圧の小さい低増倍
率動作では、光吸収領域の空乏化が不完全であって量子
効率が低く、また応答速度も低い。一方、逆バイアスを
十分大きくした高増倍率動作においては、トンネル電流
の増大による暗電流の増大が見られ、またなだれ増倍に
起因する過剰雑音の増大が見られる。これらの問題を図
面を用いて少し詳しく説明する。However, there are still problems to be solved in this SAM-APD. That is, in low multiplication factor operation with a small reverse bias voltage, the light absorption region is incompletely depleted, resulting in low quantum efficiency and low response speed. On the other hand, in high multiplication factor operation with a sufficiently large reverse bias, an increase in dark current due to an increase in tunnel current is observed, and an increase in excess noise due to avalanche multiplication is observed. These problems will be explained in some detail using drawings.
第５図は従来のＩｎＧａＡＳ／ＩｎＰを用いたＳＡＭ−
ＡＰＤの代表的構造例である。この構造は、ｎ＋型１ｎ
Ｐ基板３０１上にｎ−型１ ｎＧａＡｓ光吸収層３０２
、ｎ型１ｎＧａＡｓＰバンド障壁緩和層３０３、ｎ！１
ＩｎＰなだれ増倍層３０４、ｎ−型ＩｎＰエツジブレー
クダウン防止用低キャリア濃度層３０５を順次エピタキ
シャル成長し、Ｂｅ＋イオン注入注入ｐ−ガードリング
層３０６ｄ拡拡散型型層３０７形成し、上下の電極３０
８．３０９と無反射コート層３１０を形成して実現され
る。Figure 5 shows a conventional SAM using InGaAS/InP.
This is a typical structural example of an APD. This structure is n+ type 1n
N-type 1 nGaAs light absorption layer 302 on P substrate 301
, n-type 1nGaAsP band barrier relaxation layer 303, n! 1
An InP avalanche multiplication layer 304 and an n-type InP edge breakdown prevention low carrier concentration layer 305 are epitaxially grown in sequence, a Be+ ion implantation p- guard ring layer 306d and a diffusion type layer 307 are formed, and the upper and lower electrodes 30 are formed.
This is realized by forming 8.309 and a non-reflective coating layer 310.
第６図はこのＳＡＭ−ＡＰＤの動作原理を説明するため
のバンド構造図である。図中、実線は逆バイアス電圧を
大きくした高増倍率使用時であり、破線は逆バイアス電
圧の小さい低増倍率使用時である。このＳＡＭ−ＡＰＤ
では、逆バイアス電圧を加えて行くと先ずなだれ増倍層
３０４が空乏化し、空乏層が光吸収層３０２に達した後
光吸収層３０２の空乏化が起こる。そして光吸収層３０
２の空乏層で発生した光励起キャリアのうち電子は電界
によりＩｎＰ基板３０１へ抜け、正孔はなだれ増倍層３
０４ヘトリフトして増倍を受ける。このとき低増倍率使
用の状態では、光吸収層３０２が十分に空乏化せず、空
乏層端から正孔の拡散長以上間れた点で発生した正孔は
電流として外部へ取り出される前に再結合して消滅する
ので、量子効率が低くなってしまう。また光吸収層３０
２が十分空乏化していない状態で空乏層外で発生した正
孔は空乏層端に達するまでは拡散により律速されるから
、この拡散電流が多い低増倍率使用時は応答速度が遅い
ものとなる。また光吸収層３０２となだれ増倍層３０４
の間にはへテロ接合が存在する。ヘテロ接合近傍の電界
が十分轟ければ、正孔は電界から大きい運動エネルギを
得るのでこのヘテロ接合のバンド障壁を越えることがで
きる。FIG. 6 is a band structure diagram for explaining the operating principle of this SAM-APD. In the figure, the solid line indicates when a high multiplication factor is used with a large reverse bias voltage, and the broken line indicates when a low multiplication factor is used with a small reverse bias voltage. This SAM-APD
Then, when a reverse bias voltage is applied, the avalanche multiplication layer 304 is first depleted, and after the depletion layer reaches the light absorption layer 302, the light absorption layer 302 is depleted. and a light absorption layer 30
Among the photoexcited carriers generated in the depletion layer 2, electrons escape to the InP substrate 301 due to the electric field, and holes are transferred to the avalanche multiplication layer 3.
04 lift and receive multiplication. At this time, when a low multiplication factor is used, the light absorption layer 302 is not sufficiently depleted, and holes generated at a point that is longer than the hole diffusion length from the edge of the depletion layer are not taken out to the outside as a current. Since they recombine and disappear, the quantum efficiency becomes low. In addition, the light absorption layer 30
Holes generated outside the depletion layer when 2 is not sufficiently depleted are rate-limited by diffusion until they reach the edge of the depletion layer, so when using a low multiplication factor where there is a large diffusion current, the response speed will be slow. . In addition, the light absorption layer 302 and the avalanche multiplication layer 304
There is a heterozygosity between them. If the electric field near the heterojunction is strong enough, holes can gain large kinetic energy from the electric field and can cross the band barrier of the heterojunction.
しかし電界が低いと、正孔はこのバンド障壁部に一度滞
留し、トンネル効果や熱励起によりゆっくりと障壁を越
えて行くことになり、これも低増倍率使用時の応答速度
低下の原因となっている。正孔のバンド障壁部への滞留
を避けるためのへテロ接合部の電界値は、ＩｎＧａＡＳ
／ＩｎＧａＡＳＰ接合で５０〜１４０ｋｖ／３以上、Ｉ
ｎＧａＡＳＰ／ＩｎＰ接合で１００〜２２０ｋＶ／ｃ
ｓ＋以上必要であることが知られている。However, if the electric field is low, holes will stay in this band barrier once and will slowly cross the barrier due to tunneling effect or thermal excitation, which will also cause a decrease in response speed when using a low multiplication factor. ing. The electric field value of the heterojunction to avoid holes staying in the band barrier part is
/InGaASP junction, 50 to 140 kv/3 or more, I
100-220kV/c for nGaASP/InP junction
It is known that s+ or more is required.
一方、Ｉ ｎＧａＡｓやＩｎＧａＡＳＰは禁制帯幅が小
さいため、高い逆バイアス電圧を印加した高増倍率使用
時にはトンネル効果による暗電流が増加する。またＩ
ｎＧａＡｓや１ｎＧａＡｓｐＨでの正孔のなだれ増倍は
大きい過剰雑喬を発生することも知られている。そして
Ｉ ｎＧａＡｓ層や１ｎＱａＡｓＰ層でのトンネル電流
の発生やなだれ増倍を起こさないためには、各層の最大
電界即ちヘテロ界面電界をそれぞれ２００〜２５０ｋＶ
／ ｃｔｘ以下、３５０〜４００ｋＶ／ｃａ＋以下に抑
えなければならないことが知られている。このように各
ヘテロ接合の電界値には高速低電流かつ低雑音動作のた
めの許容範囲が存在するが、その範囲は十分広いもので
はないため、第５図の従来の構造では増倍率の広い範囲
に渡ってヘテロ接合電界をこの許容範囲に納めることが
できな、かった。On the other hand, since InGaAs and InGaASP have a small forbidden band width, when a high multiplication factor is used with a high reverse bias voltage applied, the dark current due to the tunnel effect increases. Also I
It is also known that avalanche multiplication of holes in nGaAs and 1nGaAspH generates large excess noise. In order to prevent tunnel current generation and avalanche multiplication in the InGaAs layer and the 1nQaAsP layer, the maximum electric field of each layer, that is, the heterointerface electric field, must be set to 200 to 250 kV.
It is known that the voltage must be kept below /ctx and below 350 to 400 kV/ca+. In this way, there is a tolerance range for the electric field value of each heterojunction for high-speed, low-current, and low-noise operation, but that range is not wide enough, so the conventional structure shown in Figure 5 has a wide multiplication factor. It was not possible to keep the heterojunction electric field within this permissible range over this range.
本発明は上記した点に鑑みなされたもので、なだれ増倍
率を大きくして高速、高感度でかつ低暗電流、低雑音の
動作を可能とした半導体受光素子を提供することを目的
とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor light-receiving element that has a large avalanche multiplication factor and can operate at high speed, high sensitivity, low dark current, and low noise.
本発明は、光励起キャリアを発生する光吸収領域と発生
したキャリアを増倍するなだれ増倍領域を分離して形成
したＳＡＭ−ＡＰＤにおいて、光吸収領域となだれ増倍
領域の間に、外部電圧を印加するための接続端子を設け
たことを特徴とする。The present invention provides a SAM-APD in which a light absorption region that generates photoexcited carriers and an avalanche multiplication region that multiplies the generated carriers are formed separately, and an external voltage is applied between the light absorption region and the avalanche multiplication region. It is characterized by providing a connection terminal for applying voltage.
本発明によれば、光吸収領域やヘテロ接合界面にかかる
電界を最適状態に保ったまま、なだれ増倍領域にかかる
電界、即ち増倍率を制御することができる。この結果、
なだれ増倍率の大きさに拘らず、高速・高感度で低暗電
流・低雑音の動作をするＳＡＭ−ＡＰＤが得られる。According to the present invention, it is possible to control the electric field applied to the avalanche multiplication region, that is, the multiplication factor, while maintaining the electric field applied to the light absorption region and the heterojunction interface in an optimal state. As a result,
Regardless of the magnitude of the avalanche multiplication factor, a SAM-APD that operates at high speed, high sensitivity, low dark current, and low noise can be obtained.
以下本発明の詳細な説明する。 The present invention will be explained in detail below.
第１図は一実施例の、ＩｎＰ／ＩｎＧａＡＳを用いたＳ
ＡＭ−ＡＰＤである。この素子は、ｐ＋型ＩｎＰ基板１
にｎ型１ｎＰなだれ増倍層２．ｎ型１ ｎ １−Ｘ Ｇ
ａｘＡ Ｓ ｙ Ｐｉ−ｙバンドギャップ緩和層３．
ｎ＋型Ｉ ｎ＋−ｕ Ｇａｕ ＡＳｖ Ｐｇ−ｖ高キャ
リア濃度層４．ｎ−型Ｉ ｎｌ−ａ Ｇ ａｓ Ａ Ｓ
ｔ Ｐｌ−を対電子バリア層５．ｎ−型１ ｎｏ、ｓ
ｓ Ｇ ａｏ、＋ｔＡｓ光吸収層５．ｎ＋型ＩｎＰキャ
ップ層７を順次エピタキシャル成長させたウェーハを用
いて形成される。ここで、Ｕ≧Ｘ、Ｓである。パッドギ
ャップ緩和層３．高キャリア濃度層４．対電子バリア層
５は積層方向に階段接合を構成するものであっても良い
し、グレーディッドな組成をもつものであってもよい。FIG. 1 shows an example of an S using InP/InGaAS.
It is AM-APD. This element consists of a p+ type InP substrate 1
n-type 1nP avalanche multiplication layer 2. n-type 1 n 1-X G
axA S y Pi-y bandgap relaxation layer 3.
n+ type I n+-u Gau ASv Pg-v high carrier concentration layer 4. n-type I nl-a Gas A S
t Pl- as an electron barrier layer 5. n-type 1 no, s
s Gao, +tAs light absorption layer 5. It is formed using a wafer on which an n+ type InP cap layer 7 is sequentially epitaxially grown. Here, U≧X, S. Pad gap relaxation layer 3. High carrier concentration layer 4. The electron barrier layer 5 may form a stepped junction in the stacking direction, or may have a graded composition.
このようなウェーハに、図示のような二段メサエッチン
グを施し、基板１裏面にｎ側オーミック電極８．ｎ＋型
１ｎＰキャップ層７の一部にｎ側オーミック電極９を形
成し、メサ中段の高キャリア濃度層４になだれ増倍領域
・光吸収領域共通のオーミック電極１０を形成し、更に
ｎ＋型１ｎＰキャップ１１７の光入射部に無反射コート
！！！１１を形成して素子が完成する。Such a wafer is subjected to two-stage mesa etching as shown in the figure, and an n-side ohmic electrode 8. is formed on the back surface of the substrate 1. An n-side ohmic electrode 9 is formed on a part of the n+ type 1nP cap layer 7, an ohmic electrode 10 common to the avalanche multiplication region and light absorption region is formed on the high carrier concentration layer 4 in the middle of the mesa, and an n+ type 1nP cap layer is formed. Anti-reflection coating on the light incidence part of 117! ! ! 11 is formed to complete the device.
高キャリア濃度層４は、外部接続端子である電極１０を
介して光吸収層６となだれ増倍１１２にそれぞれ独立に
外部電圧を印加することができるようにするために設け
られている。対電子バリア層５は、高キャリア濃度層４
を設けた結果この高キヤリア層の多数キャリアである電
子が光吸収！Ｉ６へ注入されるのを防ぐための障壁を構
成するものである。上記の例ではｎ−型としたが、ｐ−
型としても支障はない。パッドギャップ緩和層３は、＾
キャリア濃度Ｗ４となだれ増倍層２の間の禁制帯幅の差
により生じるエネルギ障壁を緩和し、光吸収層６からの
光励起キャリアである正孔の滞留を防止するためのもの
である。The high carrier concentration layer 4 is provided so that an external voltage can be applied independently to the light absorption layer 6 and the avalanche multiplier 112 via the electrode 10 which is an external connection terminal. The electron barrier layer 5 is a high carrier concentration layer 4
As a result of providing this high carrier layer, electrons, which are the majority carriers, absorb light! This constitutes a barrier to prevent injection into I6. In the above example, the n-type was used, but the p-
There is no problem as a type. The pad gap relaxation layer 3 is
This is to alleviate the energy barrier caused by the difference in the forbidden band width between the carrier concentration W4 and the avalanche multiplication layer 2, and to prevent holes, which are photoexcited carriers, from the light absorption layer 6 from staying.
第１図には、本実施例の素子を動作させるための外部結
線の一例を示している。光吸収Ｈ６やへテロ接合界面に
かかる電界は電極９と１０の間に挿入された電圧源１２
により制御される。なだれ増倍Ｗ２にかかる電界は電極
８と１０の間に挿入された電圧源１３により制御される
。光信号に比例する出力は電圧源１３に直列に接続され
た抵抗１４の両端電圧として取り出される。FIG. 1 shows an example of external connections for operating the device of this embodiment. The electric field applied to the light absorption H6 and the heterojunction interface is generated by a voltage source 12 inserted between the electrodes 9 and 10.
controlled by The electric field applied to avalanche multiplication W2 is controlled by a voltage source 13 inserted between electrodes 8 and 10. An output proportional to the optical signal is taken out as a voltage across a resistor 14 connected in series to a voltage source 13.
第２図は本実施例の素子の動作を説明するためのバンド
構造図である。実線は高増倍率使用時であり、破線は低
増倍率使用時である。第５図に示した従来例と異なり、
光吸収層６にはいずれの動作時にもほぼ一定の電界がか
かる。高キャリア濃度層４の多数キャリアである電子は
、ｎ”ｎ−接合で生じるバンドの曲りと対電子バリア層
５との間のへテロ・バンド障壁のために光吸収層６へは
流れない。無反射コート１１１１と透明なＩｎＰキャッ
プｌＩ７を通して入射した光゛ｈνは光吸収！！６で吸
収され、光励起キャリアを発生する。このうち電子はキ
ャップ１１７から電極９へと流れ、正孔は対電子バリア
層５を通って高キャリア濃度！４へ注入される。高キャ
リア濃度層４には多数の電子が存在するが、光吸収層６
と対電子バリア層５の電界で加速された正孔の大部分は
電子と再結合することなく、なだれ増倍層２へと注入さ
れる。FIG. 2 is a band structure diagram for explaining the operation of the device of this example. The solid line is when a high multiplication factor is used, and the broken line is when a low multiplication factor is used. Unlike the conventional example shown in Figure 5,
A substantially constant electric field is applied to the light absorption layer 6 during any operation. Electrons, which are majority carriers in the high carrier concentration layer 4, do not flow to the light absorption layer 6 because of the band bending that occurs at the n''n junction and the hetero band barrier between the electron barrier layer 5. Light ゛hν incident through the anti-reflection coat 1111 and the transparent InP cap 1I7 is absorbed by the light absorption!!6 and generates photo-excited carriers. Among these, electrons flow from the cap 117 to the electrode 9, and holes become counterelectrons. They are injected into the high carrier concentration layer 4 through the barrier layer 5.A large number of electrons exist in the high carrier concentration layer 4, but the light absorption layer 6
Most of the holes accelerated by the electric field of the electron barrier layer 5 are injected into the avalanche multiplication layer 2 without recombining with electrons.
バンド障壁緩和！３は、禁制帯幅の大きいなだれ増倍層
２と禁制帯幅の小さい高キャリア濃度層５の間にできる
バンド障壁に正孔が滞留して電子と再結合することによ
る。なだれ増倍！！２への正孔の注入効率の低下を防止
する働きをする。光吸収層６からの正孔の大部分が電子
と再結合せず高キャリア濃度層４を通過するのは、高キ
ャリア濃度層４が正孔の拡散長より薄く、またなだれ増
倍層２の端部が正孔の吸込み口として働くためである。Band barrier relaxation! 3 is due to holes staying in the band barrier formed between the avalanche multiplication layer 2 with a large forbidden band width and the high carrier concentration layer 5 with a small forbidden band width and recombining with electrons. Avalanche multiplication! ! This serves to prevent a decrease in the efficiency of hole injection into 2. The reason why most of the holes from the light absorption layer 6 pass through the high carrier concentration layer 4 without recombining with electrons is because the high carrier concentration layer 4 is thinner than the hole diffusion length and the avalanche multiplication layer 2 is This is because the end portion acts as a hole suction port.
これは、トランジスタでエミッタからベースに注入され
た少数キャリアがベースで殆ど再結合せずコレクタに到
達するのと同じ原理に基づく。なだれ増倍層２に注入さ
れた正孔はここでなだれ増倍を受け、ｐ＋型基板１に達
する。従って抵抗１４の両端には光入力に比例し、かつ
増倍をうけた電圧信号が得られることになる。。This is based on the same principle as that in a transistor, minority carriers injected from the emitter to the base reach the collector without almost recombining at the base. The holes injected into the avalanche multiplication layer 2 undergo avalanche multiplication here and reach the p+ type substrate 1. Therefore, a voltage signal proportional to the optical input and multiplied is obtained across the resistor 14. .
本実施例によれば、高層倍率使用時、低増倍率使用時い
ずれの場合にも高キャリア濃度層４とキャップ層７の間
の光吸収層６の電界分布とバンド構造を一定に保つこと
ができる。従って、増倍率の大きさに拘らず、光吸収層
やヘテロ接合界面の電界分布を最適化して、低雑音・低
暗電流でかつ高速・高感度の動作を行なうことができる
。またへテロ接合界面の電界を素子ごとに最適化できる
ため、製作プロセスの制御性に対する許容度を大きくと
ることができ、高性能の素子を歩留り良く作ることがで
きる。更になだれ増倍層の空乏層が高キャリア濃度層に
達する状態となるため、従来のものより低電圧で高い増
倍率を得ることができる、という利点もある。According to this embodiment, the electric field distribution and band structure of the light absorption layer 6 between the high carrier concentration layer 4 and the cap layer 7 can be kept constant regardless of whether a high multiplication factor is used or a low multiplication factor is used. can. Therefore, regardless of the magnitude of the multiplication factor, it is possible to optimize the electric field distribution in the light absorption layer and the heterojunction interface, thereby achieving high-speed, high-sensitivity operation with low noise and low dark current. Furthermore, since the electric field at the heterojunction interface can be optimized for each element, it is possible to have greater tolerance for controllability of the manufacturing process, and it is possible to manufacture high-performance elements with a high yield. Furthermore, since the depletion layer of the avalanche multiplication layer reaches a high carrier concentration layer, there is an advantage that a higher multiplication factor can be obtained at a lower voltage than in the conventional method.
第３図は、ヘテロ接合を用いないリーチスルー型５ｔ−
ＡＰＤに本発明を適用した実施例である。Figure 3 shows a reach-through type 5t-type that does not use a heterojunction.
This is an example in which the present invention is applied to an APD.
Ｓ：やＧｅなどのリーチスルー型ＡＰＤも、光吸収領域
となだれ増倍領域を分離して有しており、低増倍率では
光吸収領域が十分に空乏化せず、特性が劣化する。従っ
てこれに対しても本発明は有効である。第３図の素子は
、先ずｎ＋型Ｓｉ基板２０１にｐ−型層２０２を形成し
、その一部にイオン注入または拡散によりｐ型なだれ増
倍領域２０６を形成する。次にｐ０型高キャリア濃度層
２０３、Ｅ）−型光吸収層２０４． ｐ”型キャップ層
２０５を順次エピタキシャル成長し、その後、高キヤリ
ア濃度層電極取出し用ｐ＋型層２０７゜電１Ｉ２０８，
２０９，２１０．無反射コート層２１１、絶縁弁−離用
ＳｉＯ２埋込み層２１２などを形成して、ブレーナ構造
のＡＰＤが得られる。Reach-through type APDs such as S: and Ge also have a light absorption region and an avalanche multiplication region separately, and at a low multiplication factor, the light absorption region is not sufficiently depleted and the characteristics deteriorate. Therefore, the present invention is effective in this case as well. In the device shown in FIG. 3, first, a p- type layer 202 is formed on an n+ type Si substrate 201, and a p-type avalanche multiplication region 206 is formed in a part of the layer by ion implantation or diffusion. Next, a p0 type high carrier concentration layer 203, an E)-type light absorption layer 204. A p'' type cap layer 205 is epitaxially grown in sequence, and then a p+ type layer 207° for taking out a high carrier concentration layer electrode is formed.
209,210. By forming a non-reflective coating layer 211, an insulating valve-separating SiO2 buried layer 212, etc., an APD with a Brehner structure is obtained.
第４図はこの素子の動作を説明するためのバンド構造図
である。動作原理は先の実施例の素子と同じで、高増倍
率で使用した時（実線）も低増倍率で使用した時（破線
）も光吸収層２０４の電界を一定に維持することができ
る。従って先の実施例と同様の効果が得られる。FIG. 4 is a band structure diagram for explaining the operation of this element. The operating principle is the same as the device of the previous example, and the electric field of the light absorption layer 204 can be maintained constant both when used at a high multiplication factor (solid line) and when used at a low multiplication factor (broken line). Therefore, the same effects as in the previous embodiment can be obtained.
本発明は上記実施例に限られるものではなく、その趣旨
を逸脱しない範囲で種々変形実施することができる。The present invention is not limited to the above-described embodiments, and can be modified in various ways without departing from the spirit thereof.
第１図は本発明の−実施例のＩｎＰ／ＩｎＧａＡＳを用
いたＳＡＭ−ＡＰＤを示す図、第２図は、その動作を説
明するためのバンド構造図、第３図は他の実施例のＳ
１−ＡＰＤを示す図、第４図はその動作を説明するため
の図、第５図は従来のＳＡＭ−ＡＰＤを示す図、第６図
はその動作を説明するためのバンド構造図である。
ｉ ・ｐ＋型１ｎＰ基板、２−ｎ Ｉ Ｉ ｎ Ｐなだ
れ増倍層、３・・・ｎ型１ｎＧａＡｓＰバンドギャップ
緩和層、４・・・ｎ＋型１ ｎＧａＡｓＰ高キャリア濃
度層、５・・・ｎ型１ｎＧａＡｓＰ対電子バリア層、６
・・・ｎ−型１ ｎＧａＡｓ光吸収層、７・・・ｎ＋型
ＩｎＰキャップ層、８．９．１０・・・オーミック電極
、１１・・・無反射コート層、１２．１３・・・電圧源
、１４・・・抵抗、１５・・・出力端子、２０１・・・
ｎ４″型５ｉ基板、２０２・・・ｐ−型層、２０３・・
・ｐ＋型高キャリア濃度層、２０４・・・ｐ−型光吸収
層、２０５・・・ｐ＋型キャップ層、２０６・・・なだ
れ増倍領域、２０７・・・電極取出し用ｐ＋型層、２０
８゜２０９．２１０・・・オーミック電極、２１１・・
・無反射コート層。
第１ｉ、Ｌ
第３図
第４図
Ｚ（ＪｌFIG. 1 is a diagram showing a SAM-APD using InP/InGaAS according to an embodiment of the present invention, FIG. 2 is a band structure diagram for explaining its operation, and FIG. 3 is a SAM-APD of another embodiment.
1-APD, FIG. 4 is a diagram for explaining its operation, FIG. 5 is a diagram for explaining the conventional SAM-APD, and FIG. 6 is a band structure diagram for explaining its operation. i/p+ type 1nP substrate, 2-n I I n P avalanche multiplication layer, 3...n type 1nGaAsP band gap relaxation layer, 4...n+ type 1nGaAsP high carrier concentration layer, 5...n type 1nGaAsP vs. electron barrier layer, 6
. . . n-type 1 nGaAs light absorption layer, 7 . , 14...Resistor, 15...Output terminal, 201...
N4'' type 5i substrate, 202...p-type layer, 203...
・p + type high carrier concentration layer, 204... p - type light absorption layer, 205... p + type cap layer, 206... avalanche multiplication region, 207... p + type layer for electrode extraction, 20
8゜209.210...Ohmic electrode, 211...
・Non-reflective coating layer. Figure 1i, L Figure 3 Figure 4 Z (Jl
Claims (6)
れた半導体受光素子において、前記光吸収領域となだれ
増倍領域の中間に外部接続端子を設けたことを特徴とす
る半導体受光素子。(1) A semiconductor light receiving element in which a light absorption region and an avalanche multiplication region are formed separately, and an external connection terminal is provided between the light absorption region and the avalanche multiplication region. .
記光吸収領域となだれ増倍領域の中間にこれら二領域と
同じ導電型の高キャリア濃度層を有する特許請求の範囲
第１項記載の半導体受光素子。(2) A high carrier concentration layer having the same conductivity type as those of the light absorption region and the avalanche multiplication region is provided between the light absorption region and the avalanche multiplication region as a layer for leading out the external connection terminal. Semiconductor photodetector.
増倍領域のそれより小さい特許請求の範囲第１項記載の
半導体受光素子。(3) The semiconductor light-receiving device according to claim 1, wherein the forbidden band width of the main portion of the light absorption region is smaller than that of the avalanche multiplication region.
記光吸収領域となだれ増倍領域の中間にこれら二領域と
同じ導電型の高キャリア濃度層を有し、かつこの高キャ
リア濃度層の前記光吸収領域側の端部にこの高キャリア
濃度層の多数キャリアに対するエネルギ障壁を有する特
許請求の範囲第１項記載の半導体受光素子。(4) As a layer for leading out the external connection terminal, a high carrier concentration layer of the same conductivity type as those of the light absorption region and the avalanche multiplication region is provided between the light absorption region and the avalanche multiplication region; 2. The semiconductor light-receiving device according to claim 1, further comprising an energy barrier for majority carriers in the high carrier concentration layer at an end portion on the light absorption region side.
記光吸収領域となだれ増倍領域の中間にこれら二領域と
同じ導電型でその禁制帯幅がなだれ増倍領域のそれより
小さい高キャリア濃度層を有し、かつこれら高キャリア
濃度層となだれ増倍領域の間に両者の禁制帯幅の差によ
り生じるエネルギ障壁を緩和する領域を有する特許請求
の範囲第１項記載の半導体受光素子。(5) As a layer for leading out the external connection terminal, a high carrier is provided between the light absorption region and the avalanche multiplication region, which has the same conductivity type as these two regions and whose forbidden band width is smaller than that of the avalanche multiplication region. 2. The semiconductor light-receiving device according to claim 1, which has a concentration layer and a region between the high carrier concentration layer and the avalanche multiplication region to alleviate an energy barrier caused by a difference in forbidden band width between the two.
しい特許請求の範囲第１項記載の半導体受光素子。(6) The semiconductor light-receiving device according to claim 1, wherein the light absorption region and the avalanche multiplication region have the same forbidden band width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60010471A JPH0732264B2 (en) | 1985-01-23 | 1985-01-23 | Semiconductor light receiving element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60010471A JPH0732264B2 (en) | 1985-01-23 | 1985-01-23 | Semiconductor light receiving element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61170079A true JPS61170079A (en) | 1986-07-31 |
| JPH0732264B2 JPH0732264B2 (en) | 1995-04-10 |
Family
ID=11751055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60010471A Expired - Lifetime JPH0732264B2 (en) | 1985-01-23 | 1985-01-23 | Semiconductor light receiving element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0732264B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002203986A (en) * | 2000-12-19 | 2002-07-19 | Korea Electronics Telecommun | Avalanche photodetector |
| US6534783B1 (en) * | 1989-12-27 | 2003-03-18 | Raytheon Company | Stacked multiple quantum well superlattice infrared detector |
| WO2005078809A1 (en) * | 2004-02-13 | 2005-08-25 | Nec Corporation | Semiconductor photodetector |
| EP2856505A4 (en) * | 2012-05-29 | 2016-02-24 | Hewlett Packard Development Co | Devices including independently controllable absorption region and multiplication region electric fields |
| JP2017054911A (en) * | 2015-09-09 | 2017-03-16 | リコーイメージング株式会社 | Imaging element and imaging device |
| JP2017168610A (en) * | 2016-03-16 | 2017-09-21 | 日本電信電話株式会社 | Light-receiving element |
| CN112531067A (en) * | 2020-12-02 | 2021-03-19 | 吉林大学 | Germanium-silicon avalanche photodetector |
| US10978503B2 (en) | 2018-09-19 | 2021-04-13 | Canon Kabushiki Kaisha | Light detection apparatus, photoelectric conversion system, and movable body |
-
1985
- 1985-01-23 JP JP60010471A patent/JPH0732264B2/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6534783B1 (en) * | 1989-12-27 | 2003-03-18 | Raytheon Company | Stacked multiple quantum well superlattice infrared detector |
| JP2002203986A (en) * | 2000-12-19 | 2002-07-19 | Korea Electronics Telecommun | Avalanche photodetector |
| WO2005078809A1 (en) * | 2004-02-13 | 2005-08-25 | Nec Corporation | Semiconductor photodetector |
| US7560751B2 (en) | 2004-02-13 | 2009-07-14 | Nec Corporation | Semiconductor photo-detecting element |
| EP2856505A4 (en) * | 2012-05-29 | 2016-02-24 | Hewlett Packard Development Co | Devices including independently controllable absorption region and multiplication region electric fields |
| US9490385B2 (en) | 2012-05-29 | 2016-11-08 | Hewlett Packard Enterprise Development Lp | Devices including independently controllable absorption region and multiplication region electric fields |
| JP2017054911A (en) * | 2015-09-09 | 2017-03-16 | リコーイメージング株式会社 | Imaging element and imaging device |
| JP2017168610A (en) * | 2016-03-16 | 2017-09-21 | 日本電信電話株式会社 | Light-receiving element |
| US10978503B2 (en) | 2018-09-19 | 2021-04-13 | Canon Kabushiki Kaisha | Light detection apparatus, photoelectric conversion system, and movable body |
| CN112531067A (en) * | 2020-12-02 | 2021-03-19 | 吉林大学 | Germanium-silicon avalanche photodetector |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0732264B2 (en) | 1995-04-10 |
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