JPS6072054A - Double buffer memory device - Google Patents

Abstract

PURPOSE:To reduce the number of parts of a circuit by always supplying a write permitting signal to at least one write exclusive memory of two memories, and applying a memory selecting signal when writing a data. CONSTITUTION:Write data signal lines 11, 21, address signal lines 12, 22, memory selecting signal lines 13, 23 and write permitting signal lines 14, 24 are connected to plural, for instance, two memories 1, 2, respectively. Subsequently, a write data signal WD to a write exclusive memory side, and a write data signal RD to a write-read-out memory side are applied to write data selecting circuits D1, D2 connected to the lines 11, 12, respectively, and one and the other of said signals are sent out to the memory 1 and the memory 2, respectively, by a double buffer selecting signal SEL. Also, a write permitting signal WP to the write exclusive side memory is always set into a write permitted state; read-out data signals 1', 2' are connected by wired OR, and a selecting circuit is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has a draw-only memory for data storage and a memory for 1, Ui, and tx3 for data processing, and the simultaneous operation of the common memory and the function switching of both memories. This paper relates to a double-buffer memory system that can be used.

Conventionally, in this type of double buffer memory system, the write control procedure for the write-only memory is generally to supply a memory selection signal and then supply a t-input signal within the time width of this memory selection signal. It is true. Therefore, when reading from the other read/write memory, read data is also output from the memory which is used as a write-only memory and does not use read data at that time. Therefore, it is not possible to adopt a configuration in which the read data lines of the write-only memory and the write and read memories are wired-OR connected, so a method has been adopted in which a select circuit is provided at the rear stage of both memories to select the read data. For this reason, in the case of a double buffer memory system with a large number of bits, there is a drawback that the number of circuit components increases accordingly.

Therefore, an object of the present invention is to provide a double buffer memory in which the read data selection circuit is omitted and the number of circuit components is reduced.

According to the present invention, in a double buffer memory system in which one memory is used only for writing and the other is used for writing and reading, and both of these memories can operate simultaneously, the write permission signal of the write-only side memory is always written. A double buffer memory device is obtained which is characterized in that writing is performed using the memory selection (number N) in the enabled state.

Next, the present invention will be described in detail with reference to the drawings showing one embodiment of the present invention.

In the drawing, write data signal lines 11 and 21, address signal lines 12 and 22, memory selection signals 13 and 33, and write permission signal lines 14 and 24 are connected to memories 1 and 2, respectively. Each of the signals input to memory 1 and memory 2 -J11 is transmitted through direct data select circuits D1 and D2, address select circuits A1 and A2, memory selection signal select circuits S1 and S2, and one-inclusive signal select circuit P1, respectively. and P2. On the other hand, the select circuit IJ1 sends a signal WD to the memory side for the spring.
and the stored data signal RD to the reading memory side are both given, and the double buffer select signal S
It is controlled by EL to send the signal WD to one side of the memory 1 or 2, and the signal RD to the other side of the memory 1 or 2. Other select circuits A1 and A2, 81 and S2, and Pl and P2 also have address signals WA and RA to the write-only memory side and the write/read memory side, respectively.

Memory selection signals WS and R8 and write permission signals WP and RP are applied, and distribution to memory 1 and memory 2 is performed by select @ signal SEL.

Output signal line 1' of memory 1 and force signal of memory 2 + $5
! 2' is wired-ORed and output to the outside as signal line 3.

As is clear from this figure, memory 1 and memory 2 are
It is not limited to which side is the write-only side and which side is the perfume/read memory side, and the input state of the control signal is alternately inverted depending on the polarity of the double buffer select signal SEL.

The write permission signal WP to the write-only memory is always in a write permission state. For this reason, the output data signal 1' or 2' of the memory selected as the W-input only side by the double buffer select signal SEL among the memories 2 and only the memory 11 is electrically connected. It is kept at 1c. Therefore, the data signals of the two memories 1 and 2 &! Even if 1' and 2' are wired-OR connected, the data signal from the 1-in/read-side memory is not affected by the read data from the 1-in/out-only memory. That is, read data signal line 1 of two memories 1 and 2
No select circuit is required between ' and 2' and output line 3.

Hikoo, control of the ``fif loading/reading side memory'' is performed by supplying the memory selection signal and then giving the 11 loading permission No. 46 within the application time of this signal as in the past.

As explained above, each output data signal of the double buffer memory is wired-or-concatenated by setting the single-include oJ conversion signal of the burn-only side memory of the double buffer memory to the constant write permission state fc. As a result, it is possible to delete the output data selection circuit, which has the effect of reducing the number of parts.

[Brief explanation of the drawing]

The drawings illustrate one embodiment of the invention in block diagram form and in circuit diagram form. 1.2...Memory, Dl, D2. A1. A2,
81.82゜PI, P2...Select circuit.

Claims (1)

[Claims] In a double buffer memory that has at least two memories, one of which is used as a flat/consolidated memory and the other is used as a read/concave memory, the 91-included parasitic 1 memory is always connected to the Vc eaves. 1. A double buffer memory device which supplies a fukucho signal and gives a memory trace selection time to the knee-loading dedicated memory when data is loaded.