JPS6049660A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6049660A JPS6049660A JP58157010A JP15701083A JPS6049660A JP S6049660 A JPS6049660 A JP S6049660A JP 58157010 A JP58157010 A JP 58157010A JP 15701083 A JP15701083 A JP 15701083A JP S6049660 A JPS6049660 A JP S6049660A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- integrated circuit
- semiconductor integrated
- ceramic substrate
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/647—Resistive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（ａｌ 発明の技術分野
本発明は半導体装置に係り、さらに詳しくは搭載した半
導体集積回路素子の駆動回路の終端抵抗体を同一のセラ
ミック・パッケージに形成した構成に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device, and more particularly to a configuration in which a termination resistor of a drive circuit of a mounted semiconductor integrated circuit element is formed in the same ceramic package.
（ｂ） 技術の背景
電子計算機による情報処理量の増加に伴い、処理速度の
向」二と実装の高密度化がますます要求されてきている
。(b) Background of the Technology As the amount of information processed by electronic computers increases, there is an increasing demand for faster processing speed and higher density implementation.
（ｃｌ 従来技術と問題点
高速情報処理のために電子計算機の論理回路部にはＥＣ
Ｌ−ＬＳＩが使用されており、信号の高速伝送にはＩＥ
ＣＬ−ＬＳＴの前段の駆動回路の伝送ラインにはどうし
ても終端抵抗体を配設してインピーダンスの整合をとる
必要がある。(cl. Conventional technology and problems) EC is used in the logic circuit section of electronic computers for high-speed information processing.
L-LSI is used, and IE is used for high-speed signal transmission.
It is absolutely necessary to arrange a terminating resistor in the transmission line of the drive circuit in the preceding stage of the CL-LST to match the impedance.
従来は半導体集積回路素子のパッケージの周辺に終端抵
抗体を配設していたので、終端抵抗体がプリント基板の
面積を占有し、かつ半導体集積回路素子との間の配線に
よるインピーダンスが無視できなくなってきて、高密度
実装と高速情報処理の両面から何等かの対策が緊要とな
ってきた。Conventionally, a terminating resistor was placed around the package of a semiconductor integrated circuit element, so the terminating resistor occupied the area of the printed circuit board, and the impedance due to the wiring between it and the semiconductor integrated circuit element could no longer be ignored. As such, it has become necessary to take measures from both the perspectives of high-density packaging and high-speed information processing.
（川 発明の目的
本発明は前述の点に鑑みなされたもので、必ず終端抵抗
体を伴う半導体集積回路素子に対し、その終端抵抗体の
占有面積と伝送インピーダンスを極力小にする手段を提
供しようとするものである。(Object of the Invention The present invention has been made in view of the above-mentioned points.It is an object of the present invention to provide a means for minimizing the area occupied by a terminating resistor and the transmission impedance of a semiconductor integrated circuit element that always includes a terminating resistor. That is.
ｔｅ＋ 発明の構成
上記の発明の目的は、半導体集積回路素子を収容すると
共に、外部回路接続手段を備えたセラミック・パッケー
ジ上に前記半導体集積回路素子の駆動回路の終端抵抗体
を形成し、さらに該終端抵抗体をセラミック・パッケー
ジのセラミック基板の平面に対して該セラミック基板の
厚さ方向に形成したことを特徴とする半導体装置により
容易に達成される。te+ Structure of the Invention The object of the invention described above is to form a terminating resistor of a drive circuit for the semiconductor integrated circuit element on a ceramic package which accommodates the semiconductor integrated circuit element and is provided with external circuit connection means, This can be easily achieved by a semiconductor device characterized in that the terminating resistor is formed in the thickness direction of the ceramic substrate of the ceramic package with respect to the plane of the ceramic substrate.
（ｆｌ 発明の実施例
以下本発明の実施例につき図面を参照して説明する。第
１図は本発明に基づく半導体装置の一実施例の構造を示
す断面図である。Embodiments of the Invention Examples of the present invention will now be described with reference to the drawings. FIG. 1 is a sectional view showing the structure of an embodiment of a semiconductor device according to the present invention.
セラミック基板Ｉに収容搭載された半導体集積回路素子
のチップ２は、セラミック基板１上に厚膜で形成された
ボンディングバンド３に金の細線のボンディングワイヤ
４で接続されている。ボンディングバンド３はビア５と
セラミック基板１の裏面に形成されたバンプ６よりなる
接続手段７によりプリント基板（図示せず）の配線パッ
ドに半田付けで実装接続される。A chip 2 of a semiconductor integrated circuit element housed and mounted on a ceramic substrate I is connected to a bonding band 3 formed of a thick film on the ceramic substrate 1 with a bonding wire 4 made of a thin gold wire. The bonding band 3 is mounted and connected to a wiring pad of a printed circuit board (not shown) by means of a connecting means 7 consisting of a via 5 and a bump 6 formed on the back surface of the ceramic substrate 1 by soldering.
これまでは通常のセラミックパッケージの構造であるが
２本実施例においては、セラミック基板１の側面に厚膜
法によって抵抗体８が形成され。Up to now, the structure has been a normal ceramic package, but in the second embodiment, a resistor 8 is formed on the side surface of the ceramic substrate 1 by a thick film method.
各抵抗体８の一方の端部はそれぞれにボンディングバン
ド３に接続され、他の端部は共通端子９に接続して短絡
されている。One end of each resistor 8 is connected to the bonding band 3, and the other end is connected to a common terminal 9 and short-circuited.
セラミック基板１はセラミック枠１０とセラミック蓋１
１で密閉されているので、内部の半導体集積回路素子の
チップ２は環境の塵埃や湿気から保護されている。Ceramic substrate 1 includes ceramic frame 10 and ceramic lid 1
1, the internal semiconductor integrated circuit element chip 2 is protected from environmental dust and moisture.
またセラミック基板１の側面の抵抗体８は絶縁層１３の
被覆により保護されている。Further, the resistor 8 on the side surface of the ceramic substrate 1 is protected by being covered with an insulating layer 13.
以上の構造であるから、半導体集積回路素子の各信号端
子に対し、各抵抗体８は並列に接続された上、共通端子
で接地あるいは電源に接続することになるので、該抵抗
体８を終端抵抗体として使用することが出来る。With the above structure, each resistor 8 is connected in parallel to each signal terminal of the semiconductor integrated circuit element, and is also connected to the ground or power supply through a common terminal, so the resistor 8 is used as a terminal terminal. It can be used as a resistor.
第２図はセラミック枠１０およびセラミック蓋１１を除
去した時の平面図で、半導体集積回路素子のチップ２．
ボンディングパッド３．ビア５等の関係位置を示したも
のである。FIG. 2 is a plan view with the ceramic frame 10 and the ceramic lid 11 removed, showing the chip 2 of the semiconductor integrated circuit element.
Bonding pad 3. It shows the relative positions of vias 5 and the like.
第３図は側面図で、抵抗体８と共通端子９の配置を示す
。共通端子９はセラミック基板１の裏面、 の四隅に配
設されたパン１６ｇでプリント基板（図示せず）に接続
される。FIG. 3 is a side view showing the arrangement of the resistor 8 and the common terminal 9. The common terminal 9 is connected to a printed circuit board (not shown) through pans 16g provided at the four corners of the back surface of the ceramic substrate 1.
第４図は本発明に基づ〈実施例の別の変形例を示す断面
図である。第１図の抵抗体８の代わりに。FIG. 4 is a sectional view showing another modification of the embodiment based on the present invention. In place of the resistor 8 in FIG.
セラミック基板１の底面に該セラミック基板１を貫通し
て設けられた孔に抵抗体材料を充填して焼成した抵抗体
１８を配設したものである。該抵抗体１８は前例と同様
にその一端は半導体集積回路素子の信号端子に、他端は
共通端子１９で短絡され、接地または電源接続用のリー
ド端子２０ｇに接続している。本実施例では信号端子と
してはリード端子２０が使用されている。A resistor 18 is disposed on the bottom surface of the ceramic substrate 1 by filling a hole formed through the ceramic substrate 1 with a resistor material and firing it. As in the previous example, one end of the resistor 18 is short-circuited to the signal terminal of the semiconductor integrated circuit element, and the other end is short-circuited to the common terminal 19 and connected to a lead terminal 20g for grounding or power supply connection. In this embodiment, lead terminals 20 are used as signal terminals.
第５図はさらに別の実施例を示す断面図である。FIG. 5 is a sectional view showing yet another embodiment.
本実施例ではセラミック・パッケージの占有面積を第４
図に示した実施例より一層縮小するために。In this example, the area occupied by the ceramic package is
In order to further reduce the embodiment shown in the figure.
外部回路接続手段としてビア２５とバンプ２６を採用し
たもので、終端抵抗体用の抵抗体１８はセラミック基板
１の裏面に形成された厚膜の共通端子２９で短絡された
上、バンプ２９ｇでプリント基板（図示せず）に接続さ
れる。Vias 25 and bumps 26 are used as external circuit connection means, and the resistor 18 for the terminating resistor is short-circuited with a thick film common terminal 29 formed on the back surface of the ceramic substrate 1, and then printed with bumps 29g. Connected to a substrate (not shown).
ｆｇ） 発明の効果
以上の説明から明らかなように１本発明による構造で当
該半導体集積回路素子の駆動回路に必要な終端抵抗体を
該素子のチップの極く近傍に形成することにより５回路
をコンパクトに構成することが出来る上、終端抵抗体廻
りの電気的なインピーダンスを低減出来るので、高密度
実装と高速度信号伝送の点から非常に効果的である。fg) Effects of the Invention As is clear from the above explanation, five circuits can be realized by forming the terminating resistor necessary for the drive circuit of the semiconductor integrated circuit device very close to the chip of the device in the structure according to the present invention. Since it can be configured compactly and electrical impedance around the terminating resistor can be reduced, it is very effective in terms of high-density packaging and high-speed signal transmission.
第１図〜第５図は本発明に基づく半導体装置の実施例を
示すもので、第１図〜第３図は抵抗体を基板側面に配設
した実施例の断面図、平面図および側面図、第４図と第
５図はセラミック基板を貫通して設けられた終端抵抗体
をもつ２種の実施例を示す断面図である。
図において、■はセラミック基板、２は半導体集積回路
素子のチップ、３はボンディングバソド。
５，２５ばビア、 ６，２６ばバンプ、 ７，２７ば外
部回路接続手段、 ８．１８は抵抗体、 ９，１９．２
９は共通端子、２０ばリード端子、 ６ｇ、２ｈ、２６
ｇは接地用端子をそれぞれ示す。
第１図
第３図
＠４図
第５図
１1 to 5 show an embodiment of a semiconductor device according to the present invention, and FIGS. 1 to 3 are a sectional view, a plan view, and a side view of an embodiment in which a resistor is disposed on the side surface of a substrate. , FIG. 4 and FIG. 5 are cross-sectional views showing two types of embodiments having a terminating resistor provided through a ceramic substrate. In the figure, ■ is a ceramic substrate, 2 is a chip of a semiconductor integrated circuit element, and 3 is a bonding bath. 5, 25 are vias, 6, 26 are bumps, 7, 27 are external circuit connection means, 8.18 are resistors, 9, 19.2
9 is a common terminal, 20 is a lead terminal, 6g, 2h, 26
g indicates a grounding terminal. Figure 1 Figure 3 @ Figure 4 Figure 5 Figure 1
Claims (1)
路接続手段を備えたセラミック・パッケージにおいて、
該セラミック・パッケージ内に前記半導体集積回路素子
の駆動回路の１ｉｉ８端抵抗体を形成したことを特徴と
する半導体装置。 （２、特許請求の範囲第１項において、終端抵抗体をセ
ラミック・パッケージのセラミック基板の平面に対する
当該セラミック基板の厚さ方向に形成したことを特徴と
する半導体装置。(1) In a ceramic package that houses a semiconductor integrated circuit element and is equipped with external circuit connection means,
A semiconductor device characterized in that a 1ii8-terminal resistor of a drive circuit for the semiconductor integrated circuit element is formed in the ceramic package. (2. The semiconductor device according to claim 1, wherein the terminating resistor is formed in the thickness direction of the ceramic substrate of the ceramic package with respect to the plane of the ceramic substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58157010A JPS6049660A (en) | 1983-08-26 | 1983-08-26 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58157010A JPS6049660A (en) | 1983-08-26 | 1983-08-26 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6049660A true JPS6049660A (en) | 1985-03-18 |
Family
ID=15640203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58157010A Pending JPS6049660A (en) | 1983-08-26 | 1983-08-26 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6049660A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4949163A (en) * | 1987-04-15 | 1990-08-14 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device particularly for high speed logic operations |
-
1983
- 1983-08-26 JP JP58157010A patent/JPS6049660A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4949163A (en) * | 1987-04-15 | 1990-08-14 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device particularly for high speed logic operations |
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