JPS60246466A - Communication request selecting system - Google Patents

Abstract

PURPOSE:To equalize communication generated at every group and in the group by processing a communication request of its group one by one, designating the next group if there is no request, and changing a priority order at every round with regard to the communication request in one group, too. CONSTITUTION:A bus master controller (BMC) sends out (n) pieces of polling signals for inquiring whether a communication request exists or not, (n) pieces of bus controllers (BC) through a cable driver D11 by a polling signal sending-out circuit (PRG) 21. Also, whenever the polling is started, a reset signal is outputted from a cable driver D10, and whenever this reset signal is outputted, a selecting circuit changes a priority order. Each BC counts the polling signal by a counter 33, and when its counting value coincides with its BC number, an arrival of the polling signal is transmitted to a controlling circuit 32, and transmitted to a processor communication controller (PCC) through a lower bus 2.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a communication request selection method, and particularly to a communication request selection method for a processor in a multiprocessor system configured by a plurality of groups each including a plurality of processors. Regarding the method.

(Prior Art) Generally, a multiprocessor system configured with a plurality of processors connects the processor communication channels connected to each processor to a bus (usually called a system bus) to communicate between the processors. I am having them do this.

At this time, when the number of processors increases, due to physical constraints, etc., the processors are divided into groups, and as shown in FIG.
n, --, processor communication channels pcc, o-pc connected to CCr1o to CCn7
c.

P CCXI ~ P CCn7 , --, P CC
multiple sets of no-p CCn7 to the lower system bus LSB
1. ．． LSB2o, -...-, LSB,.

(hereinafter referred to as the lower-order bus), and this bus is connected to the bus controller BC,. , Be2O, ......, BCI
10 is connected to the upper system bus USB (hereinafter referred to as the upper bus), and the upper bus is separately provided with a bus master controller BMC that manages bus usage, and communicates between processors via the hierarchical bus. I am having them do this.

(Problem to be Solved by the Invention) In a multiprocessor system configured as described above, when processing communication requests arbitrarily generated from individual processors, conventionally, all processor communication channels on the system bus are periodically Because the system scans the processors and accepts requests in a predetermined order, acceptance is biased toward specific processors, and this bias becomes even more pronounced when a hierarchical system bus is installed. There are drawbacks.

(Means for Solving the Problems) In order to solve the above problems, the present invention includes polling signal sending means that can sequentially receive reception for each processor group;
A communication request selection method in which communication requests from all processors are accepted and processed equally by means of selecting and specifying request acceptance of a processor in a group,
A multiprocessor consisting of n pass controllers connected to a higher-level bus connected to a bus master controller, and multiple processors connected to lower-level buses connected to these bus controllers via respective processor communication channels. In the system, the bus master controller
The bus controller includes polling signal sending means for sending out a polling signal of a communication request signal that includes a polling signal counting means for counting and transmitting a polling signal that matches its own number to a lower bus; the processor communication channel receives the polling signal and sends the communication request signal to the lower bus; The device includes a sending means, and a holding means for suspending sending of the communication request signal and holding the communication request in response to an instruction from the bus master controller.

(Embodiment) Figures 2, 3 and 4 respectively show an embodiment of the present invention in the multiprocessor system shown in Figure 1 above.
FIG. 2 is a block diagram of a C device, a BC device, and a PCC device.

Note that a group of processors is eight or less, and the upper bus (USB) and lower bus are each composed of a plurality of control buses and 16 data buses that correspond to each other.

The 8MC device in FIG. 2 sends a reset signal to the control bus of the upper bus (08B) 1 via the cable driver DIG, and then sends the n B MC device via the cable driver D11.
A polling signal sending circuit (PPG) 21 sends out n pulses (hereinafter referred to as polling signals) to determine the presence or absence of a communication request to the C device, and a polling signal sending circuit (PPG) 21 that sequentially switches the priority order in synchronization with the above-mentioned reset signal. a selection circuit (SFL) 22 that selects one of the communication request signals input from the data bus of the bus 1 via the cable receivers R1 to R;
A PC other than the PCC device that issued this selected communication request
Cable drivers D, -D,
A response circuit (AN8) 23, a control circuit (CTT) 24 that controls each output function circuit in these 8 MC devices, and a communication disable signal (AN8) from the BC device, BSY) to the control circuit 24.

In the BC device shown in FIG. 3, a reset signal and a polling signal are inputted from the upper level bus 10 control bus through cable receivers R and Oyohi R41, respectively, and the counted value of the polling signal after the reset signal is determined by the number When the number matches the number of your own BC device given from the sending circuit (NG) 31, this polling signal is sent to the control circuit (CTL).
32 and a counting circuit (CTR) 33 which sends the signal to the first control bus of the lower-order bus (LSB) 2 via the cable driver D41, and the control circuit 32 which controls each functional circuit in the BC device. The direction of the communication path between the data bus of the upper bus 1 and the data bus of the lower bus 2, each consisting of two sets of eight wires, is determined for each set by the combination of the high level and low level of the control lines A and B. Cable receiver R1-R8゜R9-R, 6, R
□~R,, R2, ~R36, cable driver D1~D
s, D, ~D, 6. D□～D4. A transfer direction switching circuit consisting of D9 to D and gate circuits G, , G, , G,
BSW) 34 and the communication display signal (B
OR circuit (OR) 35 that transfers SY) to the 8MC device
and an AND circuit (AND) 36.

The PCC device shown in FIG. 4 includes a data transmitting/receiving circuit (DSR) 41 that transmits and receives data to and from a processor (CC), and a method for transmitting and receiving data between the data transmitting and receiving circuit 41 and the data bus of the lower bus 2. Cable drivers D 1 to D a # D @ to switch in sets of 8 by controlling the control lines A and B of the control circuit (CTL) 44.
D18, cable receivers R1 to R,.

When there is a request from the transfer direction switching circuit (BSW) 42 consisting of R9-R16 and gate circuits G1 #G2 and the processor (CC), a polling signal is sent from the lower bus 2 via the cable receiver FL. When received, the control circuit 44 sends a communication request signal to one of the data buses assigned to it and controls various functional circuits in the PCC device, and the communication sent from the 8 MC device from the 8 data buses. It is comprised of a hold circuit (R8V) 43 that instructs the control circuit 44 to hold the communication request when it receives the disable signal, and sends a communication start signal to the control circuit 44 when the communication disable signal to other parties disappears. Furthermore, the control circuit 4
During the 4-digit communication, the communication display signal (BSY) continues to be sent to the BC device.

Next, M2.3. The operation of the embodiment will be explained with reference to FIGS. When the polling signal sending circuit 21 of the B h1C device sends out a polling signal following the reset signal, all the BC devices receive these signals sent via the upper bus 1, and the respective counting circuits 33 Counting is started, and first, since the number 1, BO2, matches its own 80 number, it notifies the control circuit 32 of the arrival of the polling signal, and also transmits this signal to the FCC device via the lower bus 2. Eight PCC devices are connected to the lower bus 2, and among these, the control device [44] of the FCC device receiving communication requests from each processor CC sends communication request signals to the data bus assigned to it. to the communication channel corresponding to one of the lines. When the control device 44 receives the polling signal, an instruction is given to the control line A, so the communication request signal is sent to the BC device via the cable drivers D, D, and the BC device also performs full control. device 32
A control line AK instruction is given, and the communication request signal is sent to the BMC device via cable receivers R21 to R1l and cable drivers IJ and -D8.

The BMC device receives this communication request signal in the selection circuit 22, and selects one of the low* signals according to the priority order at that time. When the selection circuit 22 transmits the selected one to the response circuit 23, the response circuit 23 sends a communication disable signal to the communication paths other than the one corresponding to the selected one. This disable signal is from the cable drivers D1 to D, I? of the 8MC device. , C device cable receiver Re~R
ag, cable driver D, -D36 and PCCCC
It is input to the holding circuit 43 via the devices 9 to 16. If the holding circuit 43 is given the I-Confidential Disapproval signal, it instructs the control device 44 to lower the communication request, and
If there is no instruction, wait until the other PCCCC device a (! disable signal disappears.

On the other hand, the PCC device that receives the communication disable signal lowers the communication request signal, so the ]A selection circuit 22 of the BIvlC device transmits to the control wave R24 that the communication request signal other than the selected one has been rejected, and the control device 24 response circuit 23 to stop sending out the τ telegraph disable signal. Then, the hold circuit 43 of the FCC device which did not receive the communication impossible signal learns that there are no more requests other than itself, and gives a communication start signal to the control circuit 44. Polling signal sending circuit 21 of Naori MC device
sends out one polling signal, and if there is a communication request in the FCC device group corresponding to this polling signal, the communication request is immediately received by the selection circuit 22, so the control circuit 24 instructs the selection circuit 24 to transmit this polling signal. Continue sending until the start. Also, during communication, a communication display signal is given from the FCC device to the control device 24 of the 8MC device, and the control device 2
4 does not send out the next polling signal until this communication display signal disappears. Furthermore, even if one polling signal is sent out, if the communication request signal does not arrive at the selection circuit 22, the polling signal sending circuit 21 will not be given any instructions from the control circuit 24, so the polling signal sending circuit 21 will not receive any instructions from the control circuit 24, so the polling signal is sent out at a predetermined timing. Turn off that polling signal and send out the next polling signal. In this way, when the polling signal sending circuit finishes sending out n polling signals, it issues a reset signal again and then starts sending out the first polling signal again.

(Effects of the Invention) As described in detail above, according to the present invention, based on a polling signal from the 8MC device that designates a processor group, communication requests occurring in the group are processed one by one,
If there is no communication request, the next group is immediately designated to equalize communication for each group, and communication requests within one group are also accepted by changing the priority order every time the polling signal goes through. Therefore, there is an effect that communication occurring within the group is also equalized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a multiprocessor system to which the present invention is applied, and FIGS. 2, 3, and 4 each show an embodiment of the present invention. A path master controller (8MC device) , bus controller (BC% position), and processor communication controller (
FIG. 2 is a block diagram showing an FCC device fl). 1...Upper bus (USB), 2...Lower bus (LSB), 21...Polling signal sending circuit (PPG), 22...Selection circuit (SEL
), 23...Response circuit (ANS), 24, 32
．． 44... Control circuit (CTL), 25.35.
......Order circuit (OR), 31...Number sending circuit (NG), 33...Counting times 11 & (C
TR), 34.42... Transfer direction switching circuit (B
SW), 36... logical product circuit (AND41...
...Data transmitting and receiving circuit (DSR), 43...
- Hold circuit (R8V). Figure 1 Figure 2 gC6・s

Claims (1)

[Scope of Claims] n bus controllers connected to a higher-order bus connected to a bus master controller, and a plurality of processors connected to lower-order buses connected to these bus controllers via respective processor communication channels. In a multiprocessor system consisting of
The bus controller includes a polling signal sending means for sending out a polling signal, and a selection means for selecting a processor communication channel to approve communication from communication request signals sent from the processor communication channel. The processor communication channel includes a polling signal counting means for counting and transmitting a polling signal that matches the own number to a lower bus, and a communication request signal sending means for receiving the polling signal and transmitting the communication request signal to the lower bus. and a holding means for suspending the transmission of the 14-communication request borrow sign and holding the communication request in response to an instruction from the bus master controller.