JPH03265963A - Bus controller - Google Patents

Abstract

PURPOSE:To improve the availability of a bus controller by adding '1' to a counter when a data transfer request is received from a data transfer device, selecting a data transfer device corresponding to the counter having the maximum value, and subtracting '1' from the counter corresponding to the selected data transfer device. CONSTITUTION:The data transfer devices 21-2n store the information in the data transmission buffers 213-2n3 and also give the using requests of a data bus to a bus controller 1 via the bus using request signal transmission lines 212-2n2 with use of the bus using permission signals 41-4n when the data bus using conditions are produced from the data transmission circuits 211-2n1. Based on the bus using requests, '1' is added to the counters 121-12n. A selection circuit 11 refers to the counters 121-12n to select a counter having the maximum value and subtracts '1' from a counter 12 corresponding to a selected data transfer device 21. Thus the use of the bus is permitted with preference to the data transfer devices in the order of larger request values.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus control device, and more particularly to a bus control device that gives bus use rights to a data transfer device in an information processing device using a bus structure communication system.

[Conventional technology]

Conventional methods for controlling bus use permission signals in this type of bus control device include the following.

1. Method 2: Regardless of whether there is a data transfer request from the data transfer device, data transfer devices are sequentially selected and given the right to use the bus. 2. Priority is given to the source of the bus use request signal, and the bus is used according to that order. [Problem to be Solved by the Invention] The former of the conventional bus control devices described above provides bus usage rights regardless of the bus usage frequency and priority of the data transfer device. In an unbalanced system where the bus usage frequency of the request source is type 9, the bus usage efficiency of the data transfer device that makes high demands on the bus will decrease.

Furthermore, in the latter type of conventional bus control devices, when the bus control device selects the bus use request source, the frequency of bus use of the data transfer device is not reflected, and the bus control device that uses the bus frequently Usage efficiency may decrease. In addition, it takes time to determine priorities, and during that time,
There was a drawback that buses were not used.

[Means to solve the problem]

The bus control device of the present invention includes a counter that is connected to a plurality of data transfer devices via a data bus and is provided corresponding to the data transfer device, and a counter that is connected to a plurality of data transfer devices via a data bus, and that when a data transfer request is generated from the data transfer device, the counter is means for adding "1" to the data transfer device selected by the means, means for referring to the value of the counter and selecting a data transfer device corresponding to the counter having the maximum value; and means for permitting the data transfer device selected by the means to use the data bus.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

In FIG. 1, 1 is a bus control device, 121 to 12n
11 is a counter for calculating the number of bus use requests waiting for permission to use, which is provided corresponding to the data transfer device; 11 is a selection circuit that refers to the values of the counters 121 to 12n and selects the counter having the maximum value; Reference numeral 13 denotes a bus use permission signal generation circuit that generates bus use permission signals 51 to 5n for the data transfer device selected by the selection circuit 11;
is a data reception buffer, 21 to 2n are data transfer devices,
211 to 2nl are data sending circuits; 212 to 2n2 are bus use request signal generation circuits that generate bus use request signals;
213 to 2n3 are data transmission buffers, 214 to 2n4
3 is a data bus; 41-4;
n indicates a bus use request signal, 51 to 5n indicate a bus use permission signal, and 61 to 6n indicate counter subtraction for subtracting the counters 121 to 12n, respectively.

The data transfer devices 21 to 2n are data transmission circuits 211 to 2.
When a data bus usage condition occurs at In, the information is stored in the data transmission buffers 213 to 2n3, and a bus usage request signal is sent to the bus control device 1 via the bus usage request signal lines 212 to 2n.
2 requests the use of the data bus by bus use permission signals 41 to 4n. This request causes the counters 121 to 12 to
“1” is added to n.

The selection circuit 11 refers to the counters 121 to 12n, selects the counter having the maximum value (assuming that the counter 121 is the maximum value), and sends the bus permission signal generation circuit 13 to the corresponding data transfer device 21. Use permission signal 5
Generates 1.

Upon receiving the bus use permission signal 51, the data transfer device 21 causes the data sending control circuit 214 to transfer the contents of the data sending buffer 213 to the data receiving buffer 14 via the data bus 3.

Further, the bus use permission signal generating circuit 13 decrements the counter 12 corresponding to the previously selected data transfer device 21 by 01'' and ends the operation.

With the above operation, the counter 121 in the bus control device 1
~12n stores the number of data transfer requests from the data transfer devices 21 to 2n, and by using this data to determine priority in the selection circuit 11, data transfer devices with a large amount of requests are prioritized. may be allowed to use the bus.

In addition, in FIG. 1, data transfer is performed by data transfer devices 21 to 21.
2n to the bus control device 1, the reverse can also be easily realized using a similar method.

[Effects of the Invention] As explained above, the present invention enables the bus control device to determine the amount of bus usage requested by each data transfer device by having a counter for calculating the number of bus usage requests for each data transfer device. , a bus use permission signal can be generated preferentially to a frequently used data transfer device, and an efficient bus control device can be configured.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Bus control device, 11... Selection circuit, 121-
12n...Counter, 13...Bus use permission signal generation circuit, 14...Data reception buffer, 21-2n.
...Data transfer device, 211-2nl...Data transfer circuit, 212-2n2...Bus use request signal generation circuit, 213-2n3...Data sending buffer, 214-
2n4...Data transmission control circuit, 3...Data bus.

Claims (1)

[Claims] Connected to a plurality of data transfer devices via a data bus,
In response to a data transfer request from the data transfer device,
A bus control device that allows the data transfer device to use a data bus, a counter provided corresponding to the data transfer device;
means for adding "1" to the counter when a data transfer request is issued from the data transfer device; means for referring to the value of the counter and selecting a data transfer device corresponding to the counter having the maximum value; A bus control comprising: means for subtracting "1" from the counter corresponding to the data transfer device selected by the means; and means for permitting the data transfer device selected by the means to use the data bus. Device.