JPS60212900A - Semiconductor fixed memory - Google Patents

Abstract

PURPOSE:To use a circuit having high rewriting frequency and to simplify a control circuit by forming a rewriting frequency setting circuit in a chip, and when the rewriting frequency exceeds a prescribed value, switching a memory cell block to the succeeding one. CONSTITUTION:Respective cell blocks 100-103 in the memory 1 are selected by the rewriting frequency deciding circuit 2 and the same locations in respective cell blocks are simultaneously addressed from the external. Since the maximum value N of rewriting frequency of the EEPROM is set up, the same address in the cell block 101 is newly selected after ending the Nth rewriting of the same address in the cell block 100. Said control is automatically executed by a detecting circuit 2 and a write control circuit 3. Data in respective cell blocks 100-103 are outputted through an OR circuit 4.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to an electrically erasable semiconductor fixed memory device (hereinafter referred to as E
(referred to as EPROM).

(Prior art) Conventionally, EEPR,O having a floating puffer gate structure
M performs storage by applying a high voltage of about 20 V to the control gate of the memory trough star and causing electrons to reach the floating gate from the drain through a thin oxide film formed on the drain due to the Tononel effect. ing. Therefore, as the number of times high voltage is applied, that is, the number of rewrites increases, the thin oxide film gradually deteriorates and eventually breaks down. For this reason, this EEPROM is unsuitable for applications that require frequent rewriting.

(Object of the Invention) An object of the present invention is to solve such drawbacks by providing a rewrite count determination circuit inside the chip, and switching to another memory cell block prepared in advance when the number of rewrites exceeds a certain predetermined number. An object of the present invention is to provide an EEPROM that can be used even in circuits that are frequently rewritten.

(Structure of the Invention) The EEFROM of the present invention includes an electrically rewritable memory cell block divided into a plurality of blocks, a memory cell block that is divided into a plurality of blocks, a memory cell block that is electrically rewritable, a memory cell block that can be rewritten, a memory cell block that can be rewritten, and a memory cell block that is rewritten to a memory cell block that can be rewritten. a rewrite count determination circuit that determines that the number of rewrites has become greater than a predetermined maximum number of rewrites and sequentially switches to other memory cell blocks; and an OR circuit that inputs each output of each memory cell block and outputs it to an external output terminal. Contains and consists of.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

In the figure, 1 is a memory cell portion, and in this example, 10
Four blocks numbered 0 to 103 are prepared.

Reference numeral 2 denotes a rewriting number determination circuit, of which four circuits are prepared corresponding to memory cell blocks (hereinafter referred to as cell blocks). Further, 3 is a block that controls write and read operations of the EEFROM, and 4 is an OR circuit that transmits data from each cell block to the output. Note that other components necessary for memory operation, such as an address decoder and a sense amplifier, are omitted.

Next, the operation of the main blocks will be explained. The number of rewrites determining circuit 2 is composed of a MOS transistor with a floating gate structure, which has been used in ultraviolet erasable EPROMs, and an analog comparator. The threshold voltage VTR of the MOS transistor of this circuit 2 is determined by the voltage VPP applied to the floating gate and the number of times of application N.
and is proportional to the application time t, and is expressed by the following equation.

VTR=f (vII)P r N + t) Therefore, if the voltage value of the gate voltage Vpp and the application time t are constant, the threshold voltage VTR will be proportional to the number of rewrites.

In the case of this embodiment, since the degree of margin for the maximum number of rewrites before the memory cell is destroyed is set, the accuracy of the threshold voltage VTH, that is, the accuracy of detecting the number of rewrites, does not necessarily need to be high.

Next, each cell block of the memory cell 1, which is equally divided into four blocks numbered 100, 101, 102, and 103, is selected by the rewrite count determination circuit 2, and the same location within the cell block is selected at the same time as the fc4 block. It is configured to be addressed from the outside.

If the maximum number of EEPROM rewrites is set to N, then after the Nth rewrite is completed at a certain address in the cell block 100, the same address in the cell block 101 will be newly selected next time.

A specific example in which rewriting is performed in byte units will be explained using FIG. 2.

Figure 2 shows an EEROM consisting of four blocks 100 to 103.
2 is a configuration diagram of the memory cell section of each cell block 1.
00 to 103 are made up of 8 bits.

Here, the cell block 100 indicates the state of a pattern that has been used for the maximum number of rewrites N times, and the cell block 101 indicates the state of the pattern that has been used for the maximum number of rewrites N times.
The pattern after the first write is shown in the cell block 102.
．． 103 indicates an unused state. In this cell block 100, the data at the AK address was selected to be rewritten the N+1st time, but since the maximum number of rewrites N for the cell block 100 has been exceeded, the data at the corresponding word AK is erased to 0, and then Cell block 101 is selected and data to be rewritten is written in the same word. ROM butter/ in FIG. 2 represents this state.

Next, from the N+2 to 2N times of rewriting, even if the number of rewrites of each word in the cell block 101 has not reached N, the 8-bit data corresponding to the specified address is once erased, and then the cell block is rewritten. Write data to the corresponding address of 102. All of this control can be performed automatically by the rewrite count detection circuit 2 and the write control circuit 3.

As for the method of once erasing before writing in this block, the method employed in existing EEFROMs is used.

Note that data continues to be output from each cell block 100 to 10.
Since the 8-bit data in 3 is connected to the OR circuit 4, any valid data is output.

This means that all unused cells have data "O" and 1
This is because the word once invalidated in the cell block is erased to data "0". In the above explanation, the erased state of the memory cell is assigned to logic "0", and the written state is assigned to logic rIJ.

(Effects of the Invention) As explained above, according to the present invention, when even one word is rewritten more than the maximum number of rewrites N, subsequent rewriting is performed by using a new cell block, thereby controlling the control circuit. Moreover, since the rewriting control is automatically processed inside the chip, there is no need to increase the number of external terminals, and it can be realized while maintaining terminal compatibility with conventional products.

As described above, according to the present invention, the number of times the EEPROM can be rewritten can be increased by the number of spare cell blocks, and the field of application can be expected to expand.

[Brief explanation of drawings]

FIG. 1 is a main block diagram of an embodiment of the present invention, and FIG. 2 is a ROM pattern diagram of the memory cell block of FIG. In the figure, 1... Memory cell block, 2... Rewriting number determination circuit, 3... Control circuit, 4...
...08 circuit, 100°101.102.103...
...It is a cell block divided into four equal parts.

Claims (1)

[Claims] An electrically rewritable memory cell block that is divided into a plurality of blocks, and when rewriting to one of these memory cell blocks is selected and the number of rewrites to a certain memory cell block has become greater than a predetermined maximum number of rewrites. A semiconductor fixed memory device including a rewrite count determination circuit that determines and sequentially switches to another memory cell block, and an OR circuit that inputs each output of each of the memory cell blocks and outputs it to an external output terminal.