JPS6020269A - Microcomputer system - Google Patents

Abstract

PURPOSE:To make it possible to DMA-transfer only a part of data of a certain sector in the external memory to the main memory by installing a data buffer, address counter, mu (micronistruction) control circuit and a stack register at the external memory control circuit. CONSTITUTION:The floppy disk control circuit 103 has the input/output processing circuit 108 which responds to the command from the MPU (microcomputer), data processing unit 109, buffers 110A and 110B which store data from the floppy disk, and counters 111A and 111B which supply the address to these buffers. The data processing unit 108 includes the stack register 207, mu control circuit 208 and decoder 304. The mu control circuit 208 responds to the command from the CPU, and controls counters 111A and 111B, buffers 110A and 110B, etc., by utilizing microinstruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a microcomputer system having a control circuit for an external storage device.

[Background of the invention]

Conventionally, in order to read data from a floppy disk and store this data in a random access memory (RAM) used by a microcomputer (MPU), a buffer is provided in the control circuit of the floppy disk, and the data read from the disk is stored in this buffer. After storing the RAM
was being transferred to.

The MPU performs data processing using this data, or rewrites some of the data and stores it again on the floppy disk via a buffer.

Conventionally, data was read from a disk in units of areas called sectors. Therefore, the buffer had a capacity of one sector or an integral multiple thereof. In the prior art, even when an MpU uses part of the data in one sector in a 70-tup disk, it reads out the entire contents of that sector into a buffer and then transfers it all to the RAM. Therefore, since unused data is also transferred, the data bus is occupied for unnecessary data transfer.

Furthermore, even when the MPU rewrites specific data in one sector, the entire data in that sector is transferred from the buffer to the RAM, and after the transfer, the MPU accesses the RAM and rewrites the data. Ta. Then, one entire sector's data including the modified data was stored on the disk again via the buffer. For this reason, data that does not need to be changed is also transferred to the RAM, which is a wasteful process.

From the above facts, it is desirable to configure the system so that only desired data among the data in the buffer provided in the external storage control circuit is transferred to the RAM. Also, if you want to rewrite the data in the buffer, you can directly write the buffer to M
It is desirable that the PU be able to access and rewrite it. In this case, in order to configure the external storage control circuit with an integrated circuit, it is necessary to use the signal lines used in conventional microcomputers as much as possible to achieve the above requirements. This is desirable in order not to increase the number of pins.

[Purpose of the invention]

Therefore, one object of the present invention is to provide a microcomputer system in which desired data in a buffer provided in an external storage control circuit can be selectively transferred to a RAM.

A further object of the present invention is to provide a microcomputer system that allows selective transfer of data in the buffer by using signal lines used in conventional microcomputer systems as much as possible.

[Summary of the invention]

Therefore, in the present invention, an MPU is included in the external storage control circuit.
A circuit that responds to a transfer command given by a transfer command, sets a transfer start address specified following the command to a counter giving an address for the buffer, and transfers the output of the buffer to a common bus connected to the MPU and the RAM. , and a circuit that controls the counter to count up in response to a transfer permission signal input from the direct memory access control circuit.

In addition, in order to rewrite the data in the buffer without transferring it to RAM, in connection with the rewrite command input from the MPU, a circuit that sets the rewrite address further given from the MPU to a counter that gives the address of the node. and a circuit that provides a write signal to the buffer every time rewritten data is provided from the MPU after the setting.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is an overall configuration diagram of a microcomputer system according to the present invention. In FIG. 1, a microcomputer (MPU) 101 includes a random access memory (RAM) 102 and a direct memory access (D
MA) control circuit 106 and floppy disk (FD)
107 and a common bus 1 consisting of an address bus 104, a data bus 105, and a control bus 114.
0, the %FD control circuit 103 controls access to the floppy disk 107 in response to a signal from the MPU or DMA control circuit 106. The FD control circuit 103 is an input/output processing circuit (IOPU) that controls the operation of the FD control circuit 103 in response to commands from the MPU.
108 and floppy disk 107, and other data processing units) (DPU)
109, a buffer (A) 110A for storing data from the floppy disk 107, and a buffer [F]] 110
B, and a counter (A) IIIA and a % counter (B) IIIB giving addresses to these buffers. Buffer (4), ■ is 1 of floppy disk 107
Each has a capacity for a sector. DMA control circuit 10
6 are connected to the common bus 10 through signal lines 100 and 115, respectively.

It is connected to l0PU10B and consists of a known DMA control circuit. That is, the DMA control circuit 106
01 and controls data transfer between the FD control circuit 103 and the RAM 102.

FIG. 2 shows portions of the 10PU 108 and DPU 109 that are relevant to the present invention. External decoder 303 decodes whether the address on bus 104 is assigned to l0PU, and if the result is positive, outputs chip select signal C8.

l0P0108 is external decoder 303, data bus 1
05, is connected to the control bus 114 and the signal line 115, and consists of a single integrated circuit. The internal decoder 304 receives a write/write signal from the chip select signal C81 bus 114.
Read signal R/W.

In response to the DMA transfer permission signal ACK applied from the DMA control circuit 106 via the line 115, the bus driver 2
22 data transfer direction or register stack 2
This controls the setting of data for 07.

That is, when signals C8, R, /W are both logic 1, or signal ACK is logic 1 and signal R/W is logic 0.
At this time, the bus driver 222 is controlled to be in the transmitting state.

On the other hand, when signal C8 is logic 1 and signal R/W is logic O,
Or signal ACK.

When both R/W are logic 1, the bus driver 222 is controlled to receive state. Register stack 207 is bus 1
05. It stores commands given from MP Ulol via the driver 222 or data for command execution, and includes a stack pointer (not shown) that indicates all register numbers in which data should be stored.

Microinstruction control circuit (hereinafter referred to as μ control circuit) 20
In response to this command, counter (8), G3
), buffer (5), CB), etc. using microinstructions, and has a microinstruction storage device 400, an arithmetic circuit 402%, an internal register group 404, etc., and is compatible with a known microprogram-controlled microcomputer. This will be realized.

The DPU 109 receives data read from the 707 video disk 107 serially via a line 202.
It has a bit shift register 205, and the data in this shift register 205 is transferred to the disk bus 113 in parallel.
is input to the buffer (5) or [F]) via the buffer (5) or [F]). Also, the data in buffer A or B can be transferred to the floppy disk 10.
7, data is transferred in parallel from buffer A or B to shift register 205 via disk bus 113 and transferred to floppy disk 107 via line 201. Switches SWB and 8WC respectively connect buffers A and B to disk bus 113 or internal bus 1.
This is for connecting to 12.

Note that the circuit 206 receives the read clock 203 or the write clock 20 given from the floppy disk 107.
This is a circuit that divides 4 into -8.

The output of this circuit is used to update counter 111A or 111B. Switch SWD.

SWE is for selecting the clock to be supplied to counters A and H, respectively.

The operation of the device will be specifically explained below.

(1) Read mode of data from disk to buffer MPUl0I sequentially writes the first command instructing the FD control circuit 103 to read data from the disk and the data necessary for executing this command to the FD control circuit 103. . The data required to execute the first command includes a sector identification number ID for specifying all sectors to start reading from the 70-tup disk 107, and whether the buffer to start storing the read data is buffer A or H. The buffer number BN indicating the number of sectors to be read from the floppy disk, the number SN of sectors to be read from the floppy disk, etc. are included. Note that the number of sectors 8N is 2 or less. The MPU executes a store instruction having an address assigned to the FD control circuit 108 and data representing the first command.

The MPU stores the FD on the bus 104 by executing this store instruction.
The address of the control circuit 103 is output, the first command is output to the bus 105, and the signal R/W on the bus 114 is set to logic O. The decoder 303 decodes this address and
Chip selector signal cst is output. The decoder 304 uses this chip select signal C8 and logic 0 signals R and /W.
In response to the bus driver 222? , outputs a signal a to line 305 to control the state of receiving data from bus 105.

Furthermore, the decoder 304 connects the stack 20 via line 305.
7, a signal indicating that data on the internal bus 112 should be set is input. Thus, register stack 2
07, the first command output from the MPU is set. The signal from the decoder 304 is μ control circuit 20
8 is also input.

This circuit is normally held waiting for command input,
When a signal is input in this state, it is programmed to access the top data of the stack 207.

Also, in order to make this access possible, the stack 207
Any register within is configured to be accessible by μ control circuit 208. μ control circuit 208 receives this leading data via line 312 and executes a program routine to decode which command it corresponds to. After decoding, the first microinstruction routine for executing the current first command is fully executed. Utilizing the fact that the data necessary for the execution of each command is determined in advance, it is checked at the beginning of this routine whether all the data necessary for the execution of the decoded command has been stored in the stack 207. After executing the store instruction of the first command, the MPU executes a plurality of store instructions in a predetermined order to sequentially write the above-mentioned data necessary for executing this command to the FD control circuit 103, and stores these data in the stack 207. are stored sequentially.

At this time, the stack pointer (not shown) is updated by a signal. The μ control circuit 108 controls the stack 2
Depending on the number of times the signal is input each time one piece of data is stored in the stack 207, all the necessary data can be stored in the stack 207.
You can see that it has been set to . Thereafter, the next operation is performed by the first microinstruction routine.

First, the μ control circuit 208 connects the floppy disk 107 and D
An activation signal is output to the PU via line 314. At this time, the sector identification number ID and the number of sectors SN are stored in the stack 2.
07 and sends it to the DPU via line 310. The DPU has a circuit that selects only the data specified by these data ID and SN from among the data read from the floppy disk 107 and transfers it to the line 202.

Next, the μ control circuit 208 extracts the buffer number BN from the stack 207 via the line 312 and controls the switch SWB or SWC to connect the designated buffer A or B to the disk bus 113. Furthermore, the counter A or B' corresponding to this buffer A or B
A signal CLRA or CLRB is output on one of the lines 210 to clear the signal CLRA or CLRB.

Furthermore, the switch SWD or SWE is switched to the output line side of the frequency dividing circuit 206. Further, the switch SWA is switched to the entire line 203 side.

In the DPU, a read clock 203 is generated in synchronization with the read data 202, and based on this clock signal,
This data is serially written into shift register 205. The frequency divider circuit 206 divides this clock into 1/8 and outputs a clock to a line 209. Therefore, 8
A clock 209 is output every time 8 pits of data are shifted into the bit capacity shift register 205. In response to this clock 209, the μ control circuit 208 outputs a write signal WBA or WEB to a buffer A or B designated by the MPU to a line 210. In this way, the data read from the floppy disk 1o7 is stored at the address indicated by the counter A or B. After this, counter A or B is set to + by clock 209.
1 will be given.

Thereafter, in the same manner, data read from the floppy disk 107 is stored in buffer A or B sequentially one byte at a time. At this time, the μ control circuit 208 counts the number of written bytes using the arithmetic circuit 402 and the register 404 each time it writes to buffer A or B, and writes up to the final address of buffer A or 1 dB (7). Check.

When the result of this check is positive, it is on the stack 207. It is checked whether the number of sectors SN specified by the MPU is 1 or 2. When the number of sectors SN is 1, data reading ends. When the number of sectors SN is 2, μ
Control circuit 208 clears counter B and switches s
Fully control wc or SWB, connect shift register 205 to buffer B or A, and set switch 8WE or SWD to the clock 209 side. After this, the data is stored just like writing to buffer A or B.

Thus, when one or two sectors of data have been stored in either A or B, the μ control circuit 208
4, an interrupt request IREQ is output to inform the MPU that data reading has been completed, and the stack pointer (not shown) and other circuits are returned to their initial states.

(2) Transfer mode from buffer to RAM When the MPU wants to transfer data stored in buffer A or B to all RAM, it initializes the DMA control circuit 106, that is, executes a store instruction, and performs DMA control. circuit 10
6, set the start address of the area in R and AM in which the data to be transferred is stored.

Thereafter, the MPU executes an instruction to store a second command instructing reading from buffer A or B to l0PU 108, and this command is stored in stack 207. Furthermore, %MPU initializes l0PU108. That is, the number BN of the buffer to start reading from.
, the number of bytes WN of the data to be read, and the address (sofa address BA) to start reading.
Store these data in 7. In response to the second command newly stored in the stack 207, the μ control circuit 208 reads 1 from the buffer address BAt-stack 207 and sends it to the internal bus 112. Furthermore, the buffer number BN is read from the stack 207 and a set signal 5ETA or 5ET is sent to the corresponding counter A or B.
Output B. In this way, after counter A or B is preset, switch SWB or SWC is connected to internal bus 11.
Set it on the 2nd side. As a result, the data stored in the area having the address indicated by counter A or B is read onto internal bus 112. Further, switch SWD or SWE is set to the line 115A side.

After that, the μ control circuit 208 sets I) MA transfer requests DR and EQ on the line 115B, and sends the DM transfer request via the line 115A.
It waits for the transfer permission signal ACK to be input from the A control circuit 106. That is, the DMA control circuit 106 receives the signal D
In response to the rising edge of REQ, a bus use request is output to the MPU via line 100 in FIG.
04, the transfer start address previously input from the MPU is output, and the signal R/W on the bus 114 is set to logic O. The decoder 304 has a signal ACK and a logic O signal R.
/W, it outputs a signal C to the bus driver 222 to put it in a transmission state, and also outputs a signal C to the μ control circuit 208.
A signal d indicating this is output.

On the other hand, data indicated by the address before counter A or B is already stored in buffer A or B on internal bus 112.
Since the bus driver 222 has entered the transmission state, this data is transferred to the bus 105. The RAM stores data on bus 105 in response to a logic O on signal R/W on bus 114 and an address on bus 104 . On the other hand, the ACK signal on line 115A causes counter A or B to count up via switch SWD or E, and the data at the next address is read onto internal bus 112. Further, the μ control circuit 208 responds to the signal C from the decoder 304 to
The stack 207 is programmed to count the number of bytes of data transferred to the stack 207.
It is detected whether or not the number of transferred bytes matches the number of transferred bytes WN.

When this detection result is negative, μ control circuit 208 holds the DMA transfer request DREQ on line 115B as is. On the other hand, after sending the transfer permission signal ACK to l0PU, the DMA control circuit 106 transmits the signals D R, E Q
If the result of this check is positive, the signal ACK is outputted onto the line 115A again at the timing when data storage to R and AM is completed. Signal R/W remains at logic zero. Furthermore, the RAM address output to bus 104 is set to a value one larger than the previous address.

After this, the data at the next address is transferred to buffer A in the same way.
Or it is written from B to RAM. Thereafter, data of the number of bytes specified in advance by the MPU is transferred from the buffer to the RAM in the same manner.

Note that during this transfer operation, the μ control circuit 208
Each time signal C is input from the decoder 304, it is checked whether the data having the last address in buffer A or B has been transferred.

For this reason, the μ control circuit 208 is programmed to read the buffer address in the stack 207 and internally hold an updated value each time the signal C is input.

When this final data transfer check is positive, the μ control circuit 208 clears the counter B or A, switches the switch SWC or SWB to the internal bus 112 side, switches the switch SWB or SWC to the disk bus 113 side, and further , switch SW' E or SWD to line 1
Switch to 15A side and connect switch SWD or SWE to line 2.
Switch to the 09 side. In this way, from now on, the operation of reading data from the buffer B or A side and transferring it to the RAM is performed.

As described above, the number of bytes of transferred data is
When the value specified by is reached, the μ control circuit 208
The signal DltEQ on line 115B is set to logic 0 and line 114
Interrupt signal II (, EQ, all outputs).

The DMA control circuit 106 stops sending the signal ACK, which permits the next transfer, in response to the signal EQ becoming 0. The MPU can know the end of data transfer by the signal IREQ.

As described above, the MPU can transfer data of any length starting from any address in the buffer to the RAM.

(3) Rewriting buffer white data When the MPU rewrites the data in buffer A or B, the MPU executes multiple store commands and sends a third command to the stack 207 that instructs all rewriting, and The buffer number BN% to be changed, the start buffer address BA of the data to be rewritten, and the number of bytes WN of the data to be rewritten are sequentially written in the same manner as described above. The μ control circuit 208 receives this third command from the stack 200.
In response to being set to 7, the stack 207 also reads the buffer address BA onto the internal bus 112 and instructs counter A or B in the stack 207 corresponding to the buffer number BN to be set to this address. Send all signals 5BTA or 5ETB. Furthermore, a switch SWD or SW corresponding to this counter A or B
Set E on the line 316 side. Furthermore, buffer number BN
Set the corresponding switch SWB or SWC to the internal bus side. The MPU then executes a store instruction that has the address for the FD control circuit 103 and has the data to be written to the buffer. As a result, lines 104 and 105
The address of the FD control circuit 103 and the data to be written are output to the line 114, and the signal R/W on the line 114 becomes 0.

As a result, this data is transferred to internal path 112 via bus driver 222. On the other hand, the μ control circuit 108 outputs the entire write signal WEA or WEB to the buffer A or B corresponding to the buffer number BN in the stack 207 in response to the output of the decoder 304. In this way, M.P.
Write data from U is stored in buffer A or B designated by the MPU. The μ control circuit 208 then outputs a signal UP' on line 316 that causes the counter A or B to count up. Thereafter, if the MPU sequentially executes store commands for specific data, new life data can be sequentially written into buffer A or B from buffer address BA preset in stack 207. Every time the μ control circuit outputs the write signal WEA or WEB, it checks whether the number of written data matches the number of bytes WN set in the stack 207, and the result of this check is When affirmative, the FD control circuit 103 is returned to a command waiting state.

(4) Continuous transfer mode from disk to RAM According to this embodiment, the fourth command is used to store the data read from the disk in the buffer, and then immediately transfer the data to the RAM.
It is possible to transfer this to . Furthermore, this transfer is performed by buffer A for data spanning multiple sectors.
It can be carried out continuously by repeatedly using B.

The operation at this time can be realized by performing the read mode from the disk to the buffer and the transfer mode from the buffer to the RAM in parallel.

Such a transfer mode can only be achieved with one command.

(5) Write mode from buffer to disk In this case, the writing clock 204 is generated by the DPU and is selected by the switch SWA instead of the clock 203. It is preferable that the μ control circuit 208 write data to the shift register 205 by selecting the switch SWB or SWC and connecting it to the buffer 8 or the Be disk bus 113.

〔Effect of the invention〕

As described above, according to the present invention, by providing a data buffer, an address counter, a μ control circuit, and a stack register in an external storage control circuit, one sector in an external storage device can be
It became possible to DMA transfer only the data of the section to the main memory. Furthermore, the above configuration makes it possible for the μ control circuit to rewrite the data in the data buffer to the external storage device after the microcomputer rewrites some of the data imported from the external storage device in the data buffer. . These effects significantly reduce the time the microcomputer occupies the data bus compared to conventional systems.

Furthermore, since the data buffer is provided in the external storage control circuit, there is no increase in the number of control signal lines, making it possible to connect to a conventional microcomputer system.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall configuration diagram of a microcomputer system according to the present invention, and FIG. 2 is a detailed configuration diagram of the main part of the input/output processing circuit indicated by Z in FIG.

Claims (1)

[Claims] 1. A microcomputer, a random access memory (RAM), a direct memory access (DMA) control circuit, a common bus connecting these, an external storage device, and the external storage device and the RAM. A microcomputer system comprising an external storage control circuit that controls data transfer between the internal and external storage devices, the external storage control circuit comprising an internal data bus, a counter, and a buffer that stores data read from the external storage device. means for outputting data having an address indicated by the counter out of the stored data in the buffer to the internal data bus; data transfer means that switches to a data transfer direction in response to an address and a read/write instruction signal issued by a microcomputer on the bus and a transfer permission signal from the DMA control circuit; A control means responsive to a predetermined command transferred by the transfer means and issued by the microcomputer, the control means controlling a read start address of the microcomputer to the buffer in response to the predetermined command on the internal bus. means for setting the counter; means for outputting a transfer request to the DMA control circuit; means for updating the counter in response to a transfer permission signal from the DMA control circuit; A null microcomputer system comprising: means for transmitting a signal on the common bus to notify the microcomputer of the completion of the transfer after data transfer equal to the number of transfer data to be transferred to the internal bus. 2. The control means is a plurality of registers connected to the internal bus, and each time the data transfer means performs an operation of receiving data from the common bus, the data on the internal bus is transferred to the registers. The read start address setting means reads the start address from one of the registers, sends it to the internal bus, and sends a set signal to the counter. The transfer end notification signal sending means counts the total number of updates of the counter, compares the number of transferred data set in one of the registers with the counted value, and sends the notification signal according to the comparison result. 1. A microcomputer system according to claim 1, which is transmitted. 3. The data transfer means outputs a chip select signal when the address of the common bus is an address assigned in advance to the external storage control circuit with a bus driver inserted between the common bus and the internal bus. a first decoder that receives data on the common bus; and a first decoder that receives data on the common bus when the chip select signal is being output and the read/input instruction signal indicates a first value. transfer to the internal bus, the read/write instruction signal indicates the first value, and the transfer permission signal indicates the DM
and a second decoder that controls the bus driver to send data on the internal bus to the common bus when the data is being output from the A control circuit. microcomputer system. 4. Microcomputers, random access memory (RAM), and direct memory access (DMA)
A microcomputer system comprising a control circuit, a common bus connecting these, an external storage device, and an external storage control circuit that controls data transfer between the external storage device and the RAM, the external storage The control circuit includes an internal data bus, a counter, and a buffer for storing write data of the microcomputer to the external storage device, and sends a write signal to write data on the internal bus to an address location indicated by the counter. a writing means inserted between the internal data bus and the common bus, an address issued by the microcomputer on the common bus, a read/write instruction signal, and a transfer permission signal from the DMA control circuit; a data transfer means for switching the data transfer direction in response to the internal bus; and a control means for responding to a predetermined command issued by the microcomputer transferred from the common bus to the internal bus by the transfer means, means for setting in the counter a write start address for the buffer of the microcomputer related to the predetermined command; and after the setting, each time write data is supplied from the microcomputer to the internal bus; and means for sending a write signal to the buffer. 5. The microcomputer system according to claim 4, wherein said control means further comprises means for updating said counter every time said write signal is sent.