JPS60185291A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To suppress the level of generated power supply noise without complexing the constitution of the titled device and the size and to prevent other circuit blocks from bad influence due to the power supply noise by supplying power supply voltage to respective circuit blocks through power supply lines divided by a power supply line base part. CONSTITUTION:Power supply voltage Vss is supplied to respective circuit blocks such as X address group clock generators X-CLG, phiX-CLG consisting of dynamic RAMs, a write-enable group clock generator W-CLG, a main amplifier MA, Y address group clock generators phiy-CLG, Y-CLG, and an I/O buffer DBF through power supply lines LS1-LS5 connected to a pad Ps to which the power supply voltage Vss is impressed and divided and branched near the pad Ps. Consequently, the parasitic wiring resistance of the lines LS1-LS5 is reduced and the impedance of the power supply line is reduced, so that the level of the generated power supply noise is suppressed without complexing the constitution and expanding the size and other circuit blocks are prevented from bad influence due to the generated power supply noise.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor integrated circuit technology and to a technology that is particularly effective when applied to the formation of power supply lines in semiconductor integrated circuit devices. Regarding effective techniques.

[Background Art] In semiconductor storage devices such as dynamic RAM (Ushidam Access Memory) made of MO8 integrated circuits, signal lines and power lines for each circuit are formed by single-layer wiring made of general aluminum. The power supply line was composed of a single wire, which passed through the circuit block closest to the power supply pad, and then branched out at various places toward the circuit blocks further away.

Therefore, if this is shown as an equivalent circuit, it will be as shown in FIG. 1(a), with each circuit block A, B, and C.

... is one power line connected to the power pad Ps (
Vss line) L, they were connected in series to each other via a wiring resistance r□. Therefore, the impedance of the power supply line becomes high, and the level of noise generated when each circuit block operates becomes large. For example, if a large current flows through circuit block A and noise is added to the power supply line, This noise may be transmitted to other circuit blocks B, C, . . . through the power supply line, and may have an adverse effect such as causing malfunction.

For example, suppose that in a circuit in which a relatively large current flows, such as a sense amplifier of a dynamic RAM, a current of about 100 mA flows through the common source for about 30 ns.

At this time, if the Vss line is arranged as shown in FIG. 1(a) and the wiring resistance is 5Ω, a noise of 0.5μ will be generated on the Vss line. If such a large noise is transmitted to the inverter in the output low level state as shown in Figure 2, which shares the Vss line, the source of MOS FET Q2 ( node n
1) The incoming noise is directly transmitted to the output node n2, and the noise is added to the output signal. the result,
There is a risk that the next stage inverter will malfunction.

On the other hand, in a dynamic RAM, the address buffer circuit and decoder circuit are operated based on external control signals such as the row address strobe signal RAS, column address strobe signal σX1, or write enable signal WE supplied from the outside. A timing generator as shown in FIG. 3 is provided to generate various internal control signals (timing signals) for this purpose. If the Vss line of this timing generator is shared with the Vss line of a circuit such as a sense amplifier or a decoder, noise generated in other circuits will be transmitted through the Vss line and enter the clock generator. Therefore, the clock generator mentioned above is M O
When the input signal φ of S, FET Qs is changed to high level and the node n3 is charged up, M O
S F E T Q 4 is turned on, thereby drawing out the charge from node n4 and changing the output φout to a high level. Therefore, when the input signal φ changes to high level and the charge at node n4 begins to be extracted, if noise is generated on the Vss line, the extraction of the charge from node n4 is delayed and the output φ
The timing at which Out changes is delayed. As a result, there is a risk that timing mismatch between signals in the next stage circuit may occur, causing the circuit to malfunction.

The present invention has revealed that the above-mentioned disadvantages occur.

[Objective of the Invention] - The object of the invention is to suppress the level of power supply noise generated in each circuit block that constitutes a semiconductor integrated circuit, and to prevent the generated power line noise from being transmitted to other circuit blocks and having an adverse effect. The objective is to provide wiring technology that can prevent this.

Another object of the present invention is to provide a technique for preventing the above-mentioned adverse effects of power line noise without increasing chip size or complicating wiring design.

The above and further objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, the power lines for each circuit block that constitutes a semiconductor integrated circuit are connected near the power pad (the main part of the power line).
By dividing and branching, the wiring resistance parasitic to each power supply line is reduced, the impedance of the power supply line is lowered, and the noise level is suppressed, and the noise generated in one circuit block is transmitted to other circuit blocks. to prevent the negative effects of power line noise. In addition, by applying double-layer wiring technology to the wiring of semiconductor integrated circuits, the power supply lines, which occupy an increased area by being separated from the power supply pads as described above, are placed on a separate wiring layer from other signal lines, etc. By forming such a wire, the above-mentioned purpose of facilitating the layout of the power supply line and suppressing the noise level of the power supply line by increasing the cross-sectional area and reducing the wiring resistance is achieved.

[Embodiment] FIGS. 4 to 7 show an embodiment in which the present invention is applied to a 256-pin dynamic RAM.

In this embodiment, although not particularly limited, each circuit constituting the memory is divided into circuit blocks as shown in FIG. 4 and arranged on a semiconductor substrate in the arrangement relationship shown in the figure. That is, the memory array M-ARY is divided into four memory mats MM, -MM, each having a 256x256 bit configuration, and a sense memory is provided between memory mats MM1 and MM2 and between MM3 and MM4. Amplifier circuit SA1. SA2 and SA3. SA4 and the Y-decoder circuit Y-DEC'1 sandwiched therebetween,
Y-DEC2 is arranged respectively.

Also, between memory mats MMI and MM3 and between MM2
A word line driver WD1. WD2
and WD3. A WD4 and X-decoder circuits X-D E C1 and X-D E C2 sandwiched therebetween are provided, respectively.

Furthermore, on one side (upper side in the drawing) of the memory array M-ARY is an X-address system tarock generator X-CL.
G, φx-CL G, write enable system clock generator W-CLG, main amplifier MA, and Y address system clock generator φy-CLG, Y-CI
-G and human output buffer DBF circuit blocks are provided.

Further, on the opposite side (lower side in the drawing) of the memory array M-ARY, each circuit block of an X address buffer X-ADB and a Y address buffer Y-ADB is arranged.

In this embodiment, as shown enlarged in FIG. 5, each of the circuit blocks X-CLG, φx-C
L G + W −CL G , M A , φy −
cLG, Y-CLG and Y-DEC are connected to a power supply pad Ps to which a power supply voltage Vss is applied from the outside,
In addition, a power supply voltage Vss is supplied by power supply lines Ls, 1 to Ls, 6 that are divided and branched from each other near the pad. However, if the power supply line (Vss line) is divided from the pad part and extended to each circuit block as described above, there will be many points where it intersects with each signal line and Vss line, making the layout design difficult. Therefore, in this embodiment, the power supply line (Vss
lines) are formed by the second layer of aluminum wiring.

Note that the X-decoder circuit X-DE, which is not shown in FIG.
For C, address buffers X-ADB, Y-ADB, etc., the memory array M is divided near the power supply pad Ps.
-Power line Ls□ extending downward through the side of ARY
and Lsl. A power supply voltage ss is supplied through the . In the figure, VBG is a circuit for generating substrate potential vbb.

Figures 6 and 7 show how to connect the second layer aluminum wiring (Vss line) A12 extended to supply the power supply voltage Vss to each circuit block as described above and the elements constituting the circuit. An example of this is shown using an inverter as shown in FIG.

On the semiconductor substrate 1, in the active region separated by a relatively thick field oxide film 2 called LOGO3, there are N+ diffusion layers 3a to 3a, which become the source and drain regions of the MOS F E'rQ 1 and Q2 that constitute the inverter. 3 c, is formed. The N1 diffusion layer 3b is a MOS FET
This is a region where the drains and sources of Q1 and Q2 are integrally formed.

On the main surface of the substrate between the diffusion layers 3a and 3b and 3b and 30, polysilicon gate electrodes 5a and 5b are formed via gate oxide films 4a and 4b, respectively. T Q 1 and Q2
is configured.

Further, an insulating film 6 such as a PSG film (phosphorus silicate glass film) is formed on the gate electrodes 5'a and 5b, and a first layer of aluminum wiring All is formed on this insulating film 6. There is. The input/output signal lines and the Vcc line of the MO3FETQ1-Q2 forming the inverter are formed by this aluminum wiring All. And this aluminum wiring All
However, the contact hole 7a formed in the insulating film 6
~7C, the above MO8FETQ1. The source and drain regions (3a to 3c) of Q2 are contacted.

Furthermore, in the second layer of the aluminum wiring All in the first layer, P
An interlayer insulating film 8 made of an SG film, an SOG film, etc. is formed,
A second layer of aluminum wiring A12 is formed on this interlayer insulating film 8. A Vss line is constituted by these aluminum wirings A and L2, and is connected to the source region (3
It is in contact with a signal line made of aluminum wiring All that is in contact with a). In other words, the MO constituting the above inverter
Although the second layer aluminum wiring A12 that supplies the power supply voltage Vss to the source of the 3FE T Q2 is not particularly limited,
Once it is dropped on the first layer of aluminum wiring All, the diffusion layer 3
It is designed to be connected to a. Note that a final passivation film 10 made of a nitride film or the like is formed on the aluminum wirings A and l2.

According to the embodiment described above, the power supply line (particularly the Vss line) is divided and branched from the vicinity of the power supply pad Ps, that is, from the main body, and is extended and connected to each circuit block constituting the memory. Therefore, 'lI for each circuit block
For example, if the connection state of the 'ss line is represented by any number of circuits,
As shown in figure (b), each circuit block A, B, C, .
. . . will be connected in parallel to the power supply terminal via a wiring resistance r□ by separate power supply lines. Therefore, the impedance of the Vss lines Lsl, Ls2, . . . that supply the power supply voltage Vss to each circuit block is lower than that in the case of FIG. 1(a). As a result, even if a large current momentarily flows inside each circuit block when it operates, the noise on the Vss line is smaller than that in Figure 1 (a), and each circuit block The generated power supply noise is less likely to be transmitted to other circuit blocks via the ss line, and less likely to have an adverse effect on other circuits.

Furthermore, since each of the above vSS lines is composed of a second layer of aluminum wiring formed separately from the first layer of aluminum wiring that constitutes the signal line and the Vss line, the Vss
Even if the line is divided or branched from the core, the layout of the Vss line will not become complicated.

Moreover, compared to the case shown in Fig. 1(a) in which all the power supply lines and signal lines are constructed using only the first layer of aluminum wiring, the width (cross-sectional area) of the Vss line can be increased without increasing the chip area. I can do it. As a result, the wiring resistance parasitic to the Vss line is reduced, the impedance of the Vss line is further reduced, and the noise level can be suppressed.

In addition, in the dynamic RA'M as described above, the MOS
Since the threshold voltage of the FET is set to about 0.4V, the MOSFET (for example, MO3FETQ4 in the circuit shown in Figure 3) connected to the Vss side in order to extract the charge from the precharged node in the circuit , MOSFET on the VSS side of the previous stage inverter (7 in the figure)
It is likely to be turned on by noise coming in from the Vss line through the 1MOS FET Q5). - Therefore, in the above embodiment, the power supply line is separated from the pad part by the second layer of aluminum wiring and is extended only for the Vss line, but the Vss line is not limited to this.
Similarly, for the cC line, a power supply line divided at the main part may be extended to each circuit block, or it may be configured by a second layer of aluminum wiring together with the Vss line.

8 and 9 show an embodiment in which the second layer aluminum wiring A12 is applied not only to the Vss line but also to the CC line.

Of these, FIG. 8 shows an example of the arrangement of power supply lines in the decoder circuit. In other words, in a large-capacity memory such as a 256-bit dynamic RAM, the decoder circuit is composed of hundreds of unit decoders DE Co, and only one or a few of these unit decoders are in the selected state. The other unit decoders are set to a non-selected state. In the unselected unit decoder, the output node n is once precharged. is operated to extract the charge of the Therefore, discharge is performed simultaneously in a very large number of unit decoders, and a large current is temporarily caused to flow in the decoder circuit. Also, even when precharging the decoder,
Since the precharge current flows through many unit decoders at the same time, a large current temporarily flows also into the Vcc line.

Therefore, in this embodiment, in addition to the Vss line, the Vcc line is also configured with a second layer of aluminum wiring A12 separate from the signal line, and by making the power supply line thicker, a large current can easily flow, and the discharge in the decoder In addition to increasing the speed of the precharge, the speed of precharging is also increased, and noise generation on the Vcc and Vss lines is suppressed.

Further, FIG. 9 shows an example of the wiring configuration in the sense amplifier circuit. In the dynamitter RAM, a circle is provided to the sense amplifier S for each D for each data line pair, so the number of sense amplifiers becomes very large. Furthermore, since they are operated simultaneously during reading, the current flowing through the entire circuit also increases. Therefore, in this embodiment, the Vcc line Lcc commonly connected to the latch type sense amplifier SAo and the discharge MOS FET
By configuring the common source line Lcs connected to the ground via Qa with the second layer aluminum wiring A12, the precharge and discharge times are shortened, and the noise on the Vcc and Vss lines is also reduced. ing.

Furthermore, as mentioned above, the second layer aluminum wiring A12 formed as a Vss line in the peripheral circuit can be used in the memory array part to reduce the resistance of the word line or bit line and reduce signal delay. . That is, for example, in a so-called two-intersection type memory array, the word line connects the group 1-1 of the MOSFET that constitutes the memory cell.
It is composed of a polysilicon layer integrated with the electrode, and the bit line or data line may be composed of aluminum wiring.

Therefore, as shown in FIG. 10, the bit line B is constructed from the first layer of aluminum wiring All, and connected to this through an interlayer insulating film above the word line W made of a polysilicon layer orthogonal to the bit line B. Parallel second layer aluminum wiring A ],
form 2.

By connecting the polysilicon word line W under the aluminum wiring A12 of this second layer to the polysilicon word line W at some places through the aluminum wiring AI of the first layer, the word line reinforced with the aluminum wiring is formed. I'll configure it. As a result, the resistance of the word line made of polysilicon may be lowered so that the rise and fall of the word line can be made faster.

[Effects] (1) The power line for each circuit block that makes up a semiconductor integrated circuit is divided and branched near the power supply pad (main part of the power line) and extended to each circuit block. Due to the effect that the wiring resistance parasitic to the power supply line becomes smaller and the impedance of the power supply line becomes lower,
This has the effect of suppressing the level of noise generated in the power line, and making it difficult for noise generated in one circuit block to be transmitted to other circuit blocks, thereby preventing the adverse effects of power line noise.

(2) By applying two-layer wiring technology to the wiring of semiconductor integrated circuits and being separated from the power supply pad as described above,
Since the power supply line, which occupies an increased area, is formed on a separate wiring layer from other signal lines, it is possible to set the layout of the power supply line and the cross-sectional area of the wiring separately from the layout of the signal line to a certain degree. This feature has the effect of facilitating the layout of the power supply lines, reducing wiring resistance, and suppressing the noise level of the power supply lines.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the power supply line and the signal line are made of aluminum wiring, but metal wiring other than aluminum may be used. Further, although the signal lines are formed using the second layer of aluminum wiring and the power lines are formed using the second layer of aluminum wiring, the relationship may be reversed.

[Field of Application] The above explanation mainly describes the invention made by the present inventor in terms of the field of application, which is the dynamic type M.
Although the description has been given of the application to an OS-RAM, the present invention is not limited thereto and can be applied to all semiconductor integrated circuit devices to which aluminum double-layer wiring technology can be applied.

[Brief explanation of the drawing]

Figure 1(a) is a circuit configuration diagram showing the Vss line connection method in a conventional dynamic RAM.
b) is Vs in the semiconductor integrated circuit to which the present invention is applied.
Figure 2 is a circuit diagram showing the connection method of the s line. Figure 2 is a circuit diagram explaining the influence of noise on the Vss line on the inverter that makes up the circuit block. Figure 3 is the influence of noise on the Vss line on the tarok generator. FIG. 4 is an explanatory diagram showing an example of the layout method of each circuit block when the present invention is applied to a dynamic RAM, and FIG. 5 is an explanatory diagram showing an example of the layout method of each circuit block when the present invention is applied to a dynamic RAM. FIG. 6 is an explanatory diagram showing an example of the layout method of the power supply lines (Vss line) in the case of FIG. 7 is a sectional view taken along the VI-VI line in FIG. 6, FIG. 8 is a circuit diagram showing a configuration example of a decoder circuit in a dynamic RAM to which the present invention is applied, and FIG. 9 is a cross-sectional view of the present invention. FIG. 10 is a circuit diagram showing a configuration example of a sense amplifier circuit in a dynamic RAM to which the invention is applied. FIG. 10 is a plan view showing an example of a wiring layout method in a memory array section. A, B, C...Circuit block, M-ARY...
Memory array, MMI to MM4... memory mat,
SA1 to SA4... sense amplifier circuit, Y-D E
C1, Y-D E C2...Y decoder circuit,
WD1 to WD4...word line driver, X-DEc
l-, X-DEC2...X decoder circuit, DECo
...Unit decoder, X-CLG, φX-CLG, W
-CLG, φy-CLG, Y-CLG...clock generator, VBG...substrate potential generation circuit, X-
ADB, Y-ADB...address buffer, 1...
...Semiconductor substrate, 2...Field oxide film, 3a,
3b, 3c...N+ diffusion layer (source, drain region), 4a, 4b...gate oxide film, 5a, 5b...
...Goo 1-electrode, 6...insulating film, 7a, 7b, 7
c...Contact hole, 8...Interlayer insulating film,
9... Through hole, 10... Passivation film. Figure 1 7'ss Figure 2 Figure 3 Figure 4 Figure 8 Figure 9 Figure 10

Claims (1)

[Claims] (1) In a semiconductor integrated circuit device consisting of a plurality of circuit blocks, a power supply line that is divided and branched from one power supply pad at its core extends from one power supply pad to each of the circuit blocks, and the circuit A semiconductor integrated circuit device characterized in that each block receives power supply voltage from a different power line. 2. In the case where the semiconductor integrated circuit device is an MO3 integrated circuit, the power supply line that supplies the ground potential of the circuit to each of the circuit blocks is divided at its core and extended to each circuit block. A semiconductor integrated circuit device according to claim 1. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the divided power supply line is formed of a wiring layer different from that of the signal line. 4. The semiconductor integrated circuit device is a dynamic type MO8-
Claims 1 and 2 of a RAM, characterized in that a power supply line that supplies power supply voltage to at least peripheral circuits is divided at its core and extended to each circuit block. The semiconductor integrated circuit device according to item 1 or 3.