JP3398570B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology of a triple well structure of a highly integrated semiconductor memory device, and particularly to a semiconductor memory device suitable for a well structure including a triple well below a memory cell array, a word driver and a sense amplifier. Related to effective technology.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, a triple well structure of a highly integrated semiconductor memory device is used to prevent noise from a peripheral circuit to a memory cell and to improve the performance of a MOS transistor (a well channel of 0 V shortens a short channel. M
OS can be used), and is widely used in DRAM of 64 Mbits or later as a means for strengthening electrostatic protection.

Regarding a semiconductor memory device using such a triple well structure, for example, the principle structure of the triple well is described in Japanese Patent Laid-Open No. 62-119958, and the actual structure of a 64-Mbit DRAM is special. It is disclosed in Kaihei 8-181292.
The feature of the latter technique is that the memory cell array and the lower portion of the sub-word driver or the word driver are covered with a deep well region, and the potential thereof is the boosted voltage VPP of the selected word line potential.
Is applied.

[0004]

In the semiconductor memory device using the triple well structure as described above, the present inventor pays attention to high integration of this semiconductor memory device, and particularly, memory cell array, word driver, Consider the well structure including the triple well under the sense amplifier,
The content examined by the inventor will be described below with reference to FIGS. 8 and 9.

8 and 9 show the above-mentioned Japanese Patent Laid-Open No. 8-181.
It is a top view and a sectional view of the structure indicated by 292 gazette. FIG. 8 shows the positions of the deep deep well region DW in the memory cell array MCA, the sub word driver SWD, and the sense amplifier SA by hatching. The sub word driver SWD is a driver that directly drives the memory cell array MCA in the hierarchical word line system. Further, FIG. 9 is a cross-sectional view of the sense amplifier SA (AA 'cross section), the sub word driver SWD (BB' cross section), the peripheral circuit, and the input / output circuit.

The feature of this structure is that the memory cell array MC
A and the sub word driver SWD or the lower part of the word driver is covered with the deep well region DW, and the boosted voltage VP of the selected word line potential which is the highest potential
Apply P. The sense amplifier SA is removed from the deep well region DW, the lower part thereof is a P-type semiconductor substrate P-Sub, and 0V is applied to this P-type semiconductor substrate P-Sub. The voltage VDD for operating the sense amplifier SA is applied to the N well region NW of the PMOS of the sense amplifier SA. The sub-word driver SWD and the sense amplifier SA operate at the most suitable well voltage. Memory cell array M
In CA, the junction capacitance of the bit line capacitance is reduced with a negative P-well voltage, the P-well voltage of the NMOS of the sense amplifier SA is set to 0 V, and the NMOS is operated in the state where the threshold voltage Vth does not change due to the substrate effect. . Further, since the operating voltage VPP or voltage VDD is applied to the PMOS N well region NW of the sub word driver SWD and the PMOS N well region NW of the sense amplifier SA, the PMOS also has a threshold voltage due to the substrate effect. V
There is no change in th.

However, a separating N well region NW is required to divide the P well region PW into a 0 bias portion and a negative bias portion at the boundaries on both sides of the sense amplifier SA and the memory cell array MCA. It is conceivable that the width of the isolation region increases the length of the sense amplifier SA and increases the chip area.

On the other hand, although not shown here, as disclosed in the above-mentioned Japanese Unexamined Patent Publication No. 8-181292, the entire lower portion of the memory cell array, sense amplifier, subword driver or word driver is covered with a deep well region. There may be a system in which the potential is VPP (entire deep well region). In this case, the isolation area at the boundary of the sense amplifier is unnecessary and the chip area can be reduced.
Since the N-well potential becomes high at the VPP level, which is higher than the operating voltage of the PMOS, the threshold voltage increases and the speed decreases due to the substrate effect.

Further, when the rise of the boosted voltage VPP is delayed when the power is turned on, a P voltage is applied between the VDD voltage applying section of the PMOS of the sense amplifier and the VPP voltage applying section of the N well region.
N-junction forward bias occurs, and latch-up may occur.

Therefore, an object of the present invention is to suppress the increase of the chip area while taking advantage of the triple well method, and especially in the recent DRAM of 64 Mbits or later, in order to relax the wiring pitch of metal word lines, a hierarchy is provided. Form word line system is adopted, the word driver is composed of a main word driver and a large number of sub-word drivers adjacent to a divided memory cell array, and a semiconductor memory device capable of realizing a triple well structure suitable for this system is provided. It is a thing.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, in the semiconductor memory device according to the present invention, deep deep well isolation is performed at the boundary between the sub word driver region and the memory cell array region, and the deep well region is continuously spread below the memory cell array and the sense amplifier. And the PMOS in the sense amplifier area
The operating voltage VDD is applied to the N well region of the above, and the voltage VPP is applied to the PMOS N well region of the sub word driver region.

According to this method, the chip area is the technique of covering the memory cell array of FIG. 9 and the sub word driver or the lower part of the word driver with the deep well region.
It is possible to realize a chip area that is intermediate to that of the technology for making the entire deep well region, and it is possible to maintain the original advantage of the triple well. Furthermore, the possibility of latch-up can be reduced.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, the same members are designated by the same reference numerals, and the repeated description thereof will be omitted.

1A and 1B are a layout diagram and a partially enlarged view showing a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 shows a memory cell array in the semiconductor memory device according to the present embodiment. FIG. 4 is a circuit diagram showing its peripheral circuits, FIG. 3 is a layout diagram showing a memory cell array and direct peripheral circuits, and FIG.
(a) and (b) are sectional views showing a direct peripheral circuit, and FIGS. 5 to 7 are a circuit diagram, a plan view and a sectional view showing a sub-word driver.

First, the configuration of the semiconductor memory device according to the present embodiment will be described with reference to FIG.

The semiconductor memory device of the present embodiment uses, for example, a hierarchical word line structure and a multi-divided bit line structure.
This is a 4 Mbit or 256 Mbit DRAM, and this memory chip 10 has a main row decoder area 1
1, the main word driver area 12, the column decoder area 13, the peripheral circuit / bonding pad area 14, the memory cell array 15, the sense amplifier area 16, the sub word driver area 17, the intersection area 18, etc., are formed by a known semiconductor manufacturing technique. It is formed on a semiconductor chip. In FIG. 1, the horizontal direction is the row direction (word line direction), and the vertical direction is the column direction (bit line direction).

In this DRAM, for example, as shown in FIG. 1, the memory cell array 1 is arranged on the left and right sides in the row direction of the memory chip 10 and on the upper and lower sides in the column direction.
A memory area including 5 and the like is divided and arranged. The memory regions arranged on the left side and the right side are arranged in pairs with the main row decoder region 11 arranged at the center interposed between the main word driver regions 12 corresponding to the respective memory regions.

Further, a column decoder area 13 corresponding to each memory area is arranged on the center side of the memory areas arranged on the upper side and the lower side. Further, a row address buffer, a column address buffer, and
A predecoder, a timing generation circuit, a data input / output circuit, and the like are arranged, and a bonding pad for external connection is provided.

In the memory area, a sense amplifier area 16 is arranged in the column direction of the memory cell array 15, and a sub word driver area 17 is arranged in the row direction. An intersection area 18 between the sense amplifier area 16 and the sub word driver area 17 is provided. An FX driver and a control circuit for the sense amplifier group (switch MOS transistor, etc.) are also arranged in the. With respect to this memory cell array 15, the word lines are in the row direction and the bit lines are in the column direction. It is self-evident that the invention can be used in the opposite arrangement.

Particularly, in the semiconductor memory device of the embodiment according to the present invention, the longitudinal direction of the chip is the word line direction, and in the hierarchical word type line configuration, the load capacitance of the main word line is relatively small. It is better to take the word line direction. The column selection signal line YS from the column decoder is arranged in the short side direction of the chip, which is advantageous for speeding up the access time of the column selection signal line YS-the input / output circuit IO.

FIG. 2 is a circuit diagram in which the memory cell array 15 and its peripheral circuits are simplified. The main row decoder area 11, the main word driver area 12, the column decoder area 13, the memory cell array 15 and the sense amplifier are shown. Area 16, sub-word driver area 17, intersection area 18
The circuits included in each area such as, the input circuit 51, the predecoder 52, the main amplifier 61, the output circuit 62, and the like are illustrated.

The memory cell array 15 is composed of a plurality of two-dimensionally arranged, for example, 64K-bit memory cells of 256 subword lines × 256 bit line pairs, and a main word line MWB (B is an inverted notation of MW, other The same applies to signal lines), the sub word line SW is in the horizontal direction, and the bit lines BL and B
The LB and the column selection signal line YS are arranged in the vertical direction.
The word line configuration is a hierarchical word line system, and the sense amplifier is 2
In the sub-array shared system and the overdrive system, that is, the sense amplifier drive line CSP is initially set at the voltage level of VDD and then at the voltage level of VDL for the purpose of increasing the speed.
It will be driven in stages. These are publicly known (IEEE Journ
al of Solid-State Circuit, Vol.31, No.9, Sep.1996, "A
29-ns 64-Mb DRAM with Hierarchical Array Architect
ure ") technology.

Subword driver regions 17 are placed adjacently on the left and right of the memory cell array 15, and the input of the subword driver is the main word line MWB and the predecoder line FX, and the output thereof is the subword line SW. In the intersection region 18 between the sense amplifier region 16 and the sub-word driver region 17, as shown in the figure, a sense amplifier driver (three NMOS transistors in the figure, but a PMOS transistor may be used on the charging side) or a local I.
O lines LIO, LIOB and main IO lines MIO, MIOB
And a switch transistor IOSW.

Although not shown in the figure, sense amplifier drive lines CSP and CSN, local IO lines LIO and LIOB, and main IO lines MIO and MI are further provided for higher performance.
A precharge circuit such as an OB or an FX driver may be placed. Besides these, there are an input circuit 51, a predecoder 52, a main word driver, a column decoder, a main amplifier 61, an output circuit 62, and the like. In FIG. 2, SHR1 and SHR2 are shared sense amplifier separation signal lines,
SAP1 and SAP2 are sense amplifier charge signal lines, and SAN is a sense amplifier discharge signal line.

Further, in order to reduce the power consumption and increase the reliability of fine devices, the internal step-down method is used, and the peripheral circuit is the voltage VPE.
RI (2.5 V), the memory cell storage voltage is the voltage VDL (2.
0V) and a voltage lower than the power supply voltage VDD (3.3V) are used. The input / output circuit uses the voltage VDD for the interface with the outside. As is well known, in order to write the voltage VDL to the memory cell, the voltage VPP boosted by the charge pumping operation is necessary as the selection voltage of the sub word line SW. Therefore, the voltage VPP is supplied to the operating voltage of the main word driver and the sub word driver. Plate voltage VPLT and bit line precharge voltage VBL
R supplies 1.0 V which is 1/2 of the voltage VDL. The substrate voltage VBB is -1.0V.

In this hierarchical word line structure, the word line is divided into multiple sub-word lines SW to share a set of main row decoder, main word driver, and sub-word driver by a plurality of sub-word lines SW, thereby forming a main word. The metal wiring pitch of the lines MW and MWB and the predecoder lines FX and FXB can be relaxed more than the pitch of the memory cells, and the manufacturing yield of the metal wiring can be increased.

In this hierarchical word line structure, the sub word lines SW arranged in the row direction are the outputs of the sub word driver, and the sub word driver includes the main row decoder and the main word lines MW and MWB output from the main word driver. , And the predecoder lines FX and FXB output from the FX driver are input to perform a logical operation. When the main word lines MW and MWB which are the inputs thereof are selected and the predecoder lines FX and FXB in the column direction are further selected, a certain sub-word driver outputs a high level voltage to the sub-word line SW, and The read operation and the write operation of all the memory cells connected to the sub word line SW are started.

In the read operation, by selecting the sub-word line SW by the sub-word driver and selecting the bit lines BL and BLB by the column decoder, an arbitrary memory cell in the memory cell array 15 is designated and this memory cell is selected. Data is amplified by the sense amplifier and then the local IO lines LIO and LIOB, and the main IO lines MIO and MI.
It is read by the OB and output from the output circuit 62 via the main amplifier 61. Similarly in the write operation, data can be written from the write circuit (not shown in FIG. 2 and arranged in parallel with the main amplifier 61) by designating an arbitrary memory cell by the sub word line SW and the bit lines BL and BLB. it can.

3 and 4 are a plan view and a sectional view showing a triple well basic structure according to an embodiment of the present invention. FIG. 3 is a plan view corresponding to FIG. 8 and shows the positions of the deep well region DW in the memory cell array, the sense amplifier region, and the sub word driver region by hatching. Memory cell array MCA and sense amplifier SA
A common deep well region DW is spread over the lower part of the. The lower part of the sub word driver SWD is out of the deep well region DW.

FIG. 4 is a sectional view of the sense amplifier SA and the sub word driver SWD. Each is shown including the boundary with the memory cell array MCA. Since the sense amplifier SA is arranged on the deep well region DW as shown in FIG. 4A, no isolation region is required at the boundary with the memory cell array MCA. On the other hand, sub word driver SWD
Is floated on the P-type semiconductor substrate P-Sub as shown in FIG. 4 (b), so that an isolation region is required at the boundary with the memory cell array MCA.

In the deep well region DW, for example, 3.
The voltage VDD of 3 V and the voltage VDD are applied to the N well region NW of the sense amplifier SA, and the sub word driver SW
In the N well region NW of D, for example, a voltage VPP of 4V
Is applied. The NMOS of the sense amplifier SA floats in the P well region PW like the NMOS of the memory cell array MCA, and the P well potential thereof is, for example, a negative voltage V of -1V.
Apply BB. On the other hand, N of the sub word driver SWD
The P well region PW of the MOS has the same VSS as the P-Sub.
(0V) is applied.

As a result, as compared with FIGS. 8 and 9, an isolation region for dividing the P well region PW at the boundary between the sense amplifier SA and the memory cell array MCA on both sides is not required, and the length of the sense amplifier SA is increased. Does not increase. On the other hand, at the boundary between the sub-word driver SWD and the memory cell array MCA, a separating NW is necessary, which causes an increase in the effective length of the sub-word driver SWD.

The relationship between the method for separating triple wells shown in FIGS. 3 and 4 and the circuit diagram shown in FIG. 2 will now be described.

The sub word driver SWD has, for example, C
The use of the MOS circuit has the advantage of high-speed operation as compared with the sub word driver SWD composed of only the NMOS.
It is necessary to apply the boosted voltage VPP to the N well region NW of the PMOS. On the other hand, PM in the sense amplifier SA
It is desirable to apply the VDD level to the N well region NW of the OS in order to speed up the sense amplifier operation and prevent latch-up at power-on.

The P-well voltage of the NMOS of the memory cell is required to apply the negative voltage VBB to reduce the bit line capacitance and to prevent the memory cell information from being destroyed when the bit line undershoots. It is desirable to apply 0V to the P well region PW of the NMOS from the viewpoint of making a short channel transistor and electrostatic protection.

Therefore, in order to separate the negative voltage P-well region PW below the memory cell array MCA and the 0V P-type semiconductor substrate P-Sub, the memory cell array MCA is separated.
When the lower part of the above is surrounded by the deep well region DW, there is a choice of the potential thereof to be VPP or VDD.

If the VPP level is set, the above-mentioned FIG.
As in the comparative example shown in (1), an isolation region by the N well region NW is required at the boundary between the memory cell array MCA and the sense amplifier SA, and the sense amplifier SA becomes substantially large. This leads to an increase in the length of the chip in the short side direction and a large increase in the chip area.

On the other hand, if the deep well potential is set to the VDD level, the memory cell array MCA as shown in FIG.
And the sub-word driver SWD at the boundary between the N well region NW
Therefore, the sub-word driver SWD becomes substantially large. Although the length of the chip in the long side direction increases, the chip area can be increased with a small width.

5 to 7 are a plan view and a sectional view of the circuit diagram and layout of the sub-word driver. The circuit diagram of FIG. 5 shows four sub-word lines, and the layout plan of FIG. 6 is an integrated sub-word driver layout diagram for outputting eight sub-word lines. The cross-sectional view of FIG. 7 is a cross-sectional structural view of the lower part of the gate with respect to the plan view of FIG.

In the subword driver of FIG. 5, four subword drivers are controlled by one main word line MWB and four predecoder lines FXB, FX. In the layout, 8 circuits are arranged in 1 unit as shown in FIG.
Two main word lines MWBn and MWBn + 1 and a predecoder line FXBm are arranged in a state where the pitch is relaxed in the horizontal direction. In particular, in the present invention, the PMO
S and NMOS are arranged on both sides to suppress an increase in area due to well separation.

One sub-word driver is, for example, as shown in FIG. 5, one PMOS transistor and two NM.
When the main word line MWB is Low, the predecoder line FXB is Low, and the predecoder line FX is High, the sub word line SW is High.
The level (VPP) is selected.

In the layout of this sub-word driver, as shown in FIG. 6, eight sub-word lines SW0 to SW14 are provided.
(Even number) is output, but since eight sub word lines SW1 to SW15 (odd number) are alternately wired from the left and right adjacent sub word drivers (not shown), a total of 16 sub word lines are output. SW0 to SW15
Are arranged in the vertical dimension in this figure.

In the sub word driver area, the main word line MWB of the metal 2 layer M2 and the metal 1 layer M1 are laterally arranged.
Sub word line SW runs, and metal 3 layer M3 is vertically provided.
The predecoder line FX and the power supply lines (VPP, VSS) are placed. Source / drain extraction in the sub-word driver is performed by the metal 1 layer M1. If the bit line layer is used for element-to-element connection, the metal can be two layers instead of three layers. The sub-word line output is converted from the metal 1 layer M1 to the gate layer FG at the left and right ends of the sub-word driver and sent to the memory cell array 15.

The cross section of the sub-word driver includes the boundary with the memory cell array 15 as shown in FIG.
Since the sub-word driver is floated on the P-type semiconductor substrate P-Sub, the memory cell array 1 having a triple well structure is provided.
A separation area is required at the boundary with 5. The voltage VPP is applied to the N well region NW of the sub word driver to
In the P well region PW of S, the same VSS (0
V) is applied. The details are as shown in FIG. 4 (b).

The triple well structure of the memory cell array 15 is designed to prevent noise from the peripheral circuits such as the sub-word driver and the sense amplifier to the memory cell, and to improve the performance of the MOS transistor (short channel M by well bias 0V).
OS can be used), and is widely used in DRAM of 64 Mbits or later as a means for strengthening electrostatic protection.

Therefore, according to the semiconductor memory device of the present embodiment, the memory cell array and the lower portion of the sense amplifier are spread in the deep well region to maintain the advantage of the triple well structure while maintaining the memory cell of FIG. A chip area intermediate between the technique of covering the array and the lower portion of the sub-word driver or the word driver with the deep well region and the technique of forming the entire surface in the deep well region can be realized.
Further, since the negative voltage VBB is applied to the P well region of the sense amplifier, the possibility of latch-up can be reduced.

Now, comparing this embodiment (FIG. 4) with the comparative example (FIG. 9), in FIG. 9, the direction of the short side becomes larger due to the isolation regions at both ends of the sense amplifier, while FIG.
Is long in the long side direction due to the isolation regions at both ends of the sub word driver. For example, in the configuration of FIG. 1, the number of subword drivers in the long side direction is equal to 34, and the number of sense amplifiers in the short side direction is equal to 34.

Therefore, since the length increase due to the well separation is equal in principle (5 μm per one sense amplifier or sub-word driver), it is considered that the chip size increase by 34 is 170 μm. If the increase in length is the same, the chip area becomes larger as the short side direction becomes larger. That is, if the chip area is 11.5 × 6.5≈74.8 mm ² in the whole deep well structure, then 1 in the case of FIG.
1.5 × 6.67≈76.7 mm ² , 11.6 in the case of FIG.
Since 7 × 6.5≈75.9 mm ³ , it can be seen that the structure according to the present embodiment is slightly smaller.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, in the above embodiment, 6
Although an example of a 4 Mbit or 256 Mbit DRAM or a synchronous DRAM has been described, the present invention is not limited to this, and a highly integrated DRAM having another number of bits.
, SRAM, RAM, ROM, PROM, EPRO
It is also widely applicable to other semiconductor memory devices such as M and EEPROM.

[0053]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1). Deep well isolation is performed at the boundary between the sub word driver and the memory cell array, and a deep well region is continuously laid under the memory cell array and the sense amplifier. An optimum voltage can be applied to the well region.

(2) By applying the deep well structure to the lower portion of the memory cell array and the sense amplifier, the width of the isolation region extends in the long side direction of the chip, so that the increase of the chip area can be suppressed.

(3) Since the sense amplifier is also surrounded by the deep well region, noise intrusion from the peripheral circuit to the bit line or the memory cell can be completely protected.

(4). When a negative voltage is applied to the P-well region of the sense amplifier or the memory cell, the conduction of the parasitic MOS hardly occurs, and in particular, in the shared sense amplifier system, the mutual electrical conductivity of the MOS transistors between the array and the sense amplifier is increased. It is advantageous for dynamic separation. Along with this, the threshold voltage of the latch transistor increases, but this is due to the low threshold voltage type NMO.
S is originally necessary and does not pose a problem.

(5). Between the voltage VDD and VSS, the capacitance between the deep well region and the P-type semiconductor substrate, about 15 nF serves as a decoupling capacitor between the power supplies, which can contribute to stabilization of the circuit operation. On the other hand, the number of capacitors for the voltage VPP decreases, but this is not a problem because the capacitance value required for VPP is small.

(6). Since the static electricity from the input pin easily escapes to the voltage VDD or VSS due to the capacitance between the power supply VDD and VSS, it is possible to contribute to the improvement of the electrostatic protection withstand voltage.

(7) Due to the above (1) to (6), in the highly integrated semiconductor memory device, it is possible to suppress the increase of the chip area while taking advantage of the triple well system, and particularly to the DRAM of 64 Mbits or later in recent years. It is possible to realize a triple well structure suitable for the hierarchical word line system used in.

[Brief description of drawings]

1A and 1B are a layout diagram and a partially enlarged view showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a memory cell array and its peripheral circuits in a semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is a layout diagram showing a memory cell array and a direct peripheral circuit in one embodiment of the present invention.

4 (a) and 4 (b) are cross-sectional views showing a direct peripheral circuit in one embodiment of the present invention.

FIG. 5 is a circuit diagram showing a sub-word driver in the embodiment of the present invention.

FIG. 6 is a plan view showing a sub-word driver according to the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a sub-word driver in the embodiment of the present invention.

FIG. 8 is a layout diagram showing a memory cell array and a direct peripheral circuit in a semiconductor memory device which is a premise of the present invention.

9A, 9B and 9C are sectional views showing a direct peripheral circuit in a semiconductor memory device which is a premise of the present invention.

[Explanation of symbols]

10 memory chips 11 Main row decoder area 12 Main word driver area 13 column decoder area 14 Peripheral circuit / bonding pad area 15 memory cell array 16 Sense amplifier area 17 Sub word driver area 18 intersection area 51 Input circuit 52 predecoder 61 Main amplifier 62 Output circuit MCA memory cell array SWD sub word driver SA sense amplifier MW, MWB main word line FX, FXB predecoder line SW sub word line BL, BLB Bit line YS column selection signal line LIO, LIOB Local IO line MIO, MIOB Main IO line SHR1, Shared-sense-amplifier separation signal line PCB Bit line Precharge signal line CSP, CSN sense amplifier drive line SAP1, 2 sense amplifier charge signal line SAN sense amplifier discharge signal line

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Manabu Ishimatsu 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitachi Ultra LSI Engineering Co., Ltd. (72) Inventor Ritsuji Ueda Tokyo 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Within Hitachi Super L.S.I. Engineering Co., Ltd. (72) Inventor Shigenobu Kato 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi ultra-L ・(56) Reference JP 8-181292 (JP, A) JP 9-139477 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8242 G11C 11/34 G11C 11/407 H01L 27/108

Claims (4)

(57) [Claims] 1. A semiconductor memory device using a triple well structure, wherein a deep well region is continuously buried under a plurality of memory cell arrays and a plurality of sense amplifiers.
NMOS of the memory cell array and the sense amplifier
, A negative voltage is supplied to the P-well region of the memory cell array and 0V is supplied to the NMOS P-well region of most of the peripheral circuits including the word driver, and the word line direction of the memory cell array is the long side of the chip.
And a bit line direction is a short side direction of the chip . 2. The semiconductor memory device according to claim 1 , wherein the word driver is a sub-word driver having a hierarchical word line structure, and there is no deep well region below the sub-word driver, and a PMOS N-well is provided. A semiconductor memory device characterized in that the same voltage as a word line selection voltage is supplied to a region. 3. A semiconductor memory using a triple well structure.
A device comprising a plurality of memory cell arrays and a plurality of senses.
Embed a deep well region continuously under the amplifier,
NMOS of the memory cell array and the sense amplifier
Negative voltage in the P-well region of the
Supply 0V to the NMOS P-well region of the peripheral circuit.
The word driver is a subword of a hierarchical word line structure.
Is a driver, and at the bottom of this subword driver
There is no deep well region, and the N well region of the PMOS has
The same voltage as the word line selection voltage is supplied, the sub-word driver is composed of PMOS and NMOS, and the layout of the sub-word driver is the PMO.
A semiconductor memory device in which S is arranged in the center and the NMOSs are arranged on both sides thereof on the side of the memory cell array. 4. A semiconductor memory device according to claim 1, 2 or 3, wherein the semiconductor memory device, a semiconductor memory device which is a D RAM.