JPS6016729A - Logical circuit - Google Patents

Abstract

PURPOSE:To reduce voltage noise without saturating an input transistor (TR) by using a rectifier element provided with a voltage clamp capability to an input signal voltage. CONSTITUTION:A collector potential change Vc of a drive current specifying TRQs when a signal at an input signal application terminal IN is changed largely from a low level to a high level selects a value of a voltage between the anode and cathode of a clamp diode Dc and a terminal voltage V7 approximately in a range possible for normal logical operation and sets it to be minimized. It is possible to keep a high speed logical operation without saturating an input TRQ1 to a large input amplitude and a voltage noise at a constant voltage application terminal 6 induced through a junction capacitance between the collector and base of the TRQs is reduced remarkably.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to logic circuits, and particularly to current switching type logic circuits driven by large amplitude input signals.

Conventionally, this type of logic circuit VC has an input transistor whose base is an input signal application terminal, whose collector is connected directly or through a resistor to a voltage source of ml, and whose emitter is commonly connected to the emitter of the input transistor. , a reference transistor whose collector is connected directly or through a resistor to the first voltage source and whose base is a reference voltage application terminal, and whose collector is connected to the commonly connected emitter VC and whose base is a constant voltage application terminal. There is a current switching type logic circuit which is composed of a drive current standard transistor and which takes the collector potential change of the input transistor or reference transistor as an output.

However, in this type of first-class switching logic circuit, when a large amplitude signal is applied to the input terminal V, the collector potential of the drive current regulating transistor changes from input 1 to 1.
; When the input signal changes from a low level to a low level, VC is voltage clamped by the operation of the reference transistor, but when the input signal changes from a low level to a high level, VC rises as the input potential rises, causing a large potential change. occurs. This potential change VC induces a charging current in the collector-substrate junction capacitance of the drive current regulating transistor. This charging current flows through all the input transistors (J1'), causing a transient VC excessive current to flow, leading to saturation of the input transistor, and causing the switching characteristics to change to k k'. Furthermore, a sudden change in the collector potential of the drive current regulating transistor induces a total voltage noise at the constant voltage application terminal through the entire collector-base junction capacitance, and other drive Frh currents commonly connected to this constant voltage application terminal The drive current value of the specified transistor is completely changed. Since the logic amplitude of a current switching type logic circuit is determined by the output load resistance and the drive current, it is said that a change in the IJ current value changes the logic amplitude and induces voltage noise in the valley output. It also has drawbacks.

Therefore, the object of the present invention is to alleviate the above-mentioned drawbacks in the conventional circuit, to provide excellent switching characteristics without saturating the input transistor even when a large amplitude input signal is applied, and to provide a drive current regulating voltage. An object of the present invention is to provide a logic circuit in which voltage noise to an application terminal is reduced.

According to the VC of the present invention, a first rectifying element whose cathode is a terminal for applying an input signal and whose anode is connected to a first voltage source through a full resistance, and whose base is connected to the anode of the first rectifying element. a first transistor whose collector is connected directly or through a resistor to the first voltage source; and whose emitter is commonly connected to the emitter of the first transistor, whose collector is connected directly or through a resistor a second transistor connected to the first voltage source and having a base as a first group II/' voltage application terminal;

The collector is connected to the emitter connected in common to nU,
The emitter and 7 terminals are connected to the second voltage source through a resistor, and the third transistor whose base is a constant voltage application terminal is connected to the voltage application terminal VC whose cathode is 1 and 2. and a second integer DI element whose anode is connected to the base of the first transistor.

A logic circuit is obtained in which the change in the collector level of the first or second transistor is taken out as an output.

This number 1': Light's ・I: +1 The 11th logic is s n'J The second rectifying element has the voltage clamping capacity k (nfi) for input 1 '11. ’ changes significantly from a low level to a high level, the VC
1-; What is the value of the first transistor? The voltage between the anode and the cathode of the second rectifying element is changed from the second reference voltage to the one-way voltage.
To clamp VC at th1χ position and limit potential changes,
The saturation of the first transistor due to the current VC and the voltage noise caused by the third transistor are significantly reduced.

Next, the present invention will be explained with reference to all the drawings.

Figure 1 shows a conventional current switching type logic circuit, in which the pace all input signal application terminal IN is used, and the collector is a load resistor R1'.
The input transistor Q is connected to the voltage source i vc through lr, and the emitter of input transistor Ql is connected to the emitter V of the input transistor Ql.
A reference transistor Q1 whose collector is connected to the voltage source 1 via the load resistor 2 and whose base is the reference voltage application terminal 5 is connected to the commonly connected emitter VC and whose emitter is connected to the resistor. connected to the voltage source 2 via the cable 3, with the base serving as a constant voltage application terminal 6;
This logic circuit is composed of a drive regulation transistor QsT, which takes out a negative logic high chip from the collector of the input transistor QI, and takes out a positive logic output from the collector of the reference transistor Qn.

In such a circuit, when the input signal application terminal IN changes from the low level VIL to the level "IH", VC changes from the conductive state to the cutoff state VC1 of the reference transistor QR, and the input transistor Q ! changed from the cutoff state to the conduction state, and the reference transistor QRK was flowing. Goods IJJ '/(4: Current ↓ S is the uniform input transistor Q4vc flowing I/(.Here,; Drive current regulating transistor Qs collector-substrate junction capacitance total ces, collector-base junction capacitance gold e
j(, If the reference voltage is ■5, then 1 pivot ''
” Collector city of L flow regulation transistor Qs: position change △V
c is approximately ΔVc medium VIH-Vs ・・・・・・・・・・・・
(1) becomes.

When this collector potential change Δvc occurs at short poem 11↓1 (Mut), VC is s Ce5e c, and a transient current i flows through all of C, VC, and this transient current i is approximately ΔVc i Medium ((,'cs + ejc) ・---(2) Δ
During t zn-Vs (Ccs" (-:jc) e---(3) Δt, this transient current i flows into the VC input transistor Q! at the same time as the driving current 1. is switched. (3
) As can be seen from the equation, the transient current i is the input potential change V
Since it is proportional to C, in the case of J' where the input potential change is large,
An excessive transient current flows, and the input transistor QI is forced into the saturation region VC, resulting in deterioration of the switching characteristics.

In addition, a sudden change in input potential causes a sudden change in the collector potential of the drive current regulating transistor Qs, which increases the capacitance of Cjc and induces VC voltage noise at the constant voltage application terminal 6.
Another drive current regulating transistor 1 valve is commonly connected to this constant voltage applying part 6, and each output VC of the other current switching type logic circuit is connected. li: Pressure noise? f: Inducing becomes VC.

FIG. 2 is a diagram showing a first embodiment of the present invention,
The cathode is used as the input signal application terminal IN.

Is the anode resistor R1? The input diode DI is connected to the voltage υ through the input diode DI, the conductor is connected to the anode of the input diode DI, and the collector is connected to the load resistor Rx? The input transistor Qx is connected to the voltage source 1 through the input transistor Q!, and the emitter is connected to the input transistor Q! The emitters are commonly connected to each other, the collector is connected to the voltage source IVc through the load resistor R, and
A reference transistor QB whose base is a -Ji quasi-tfl pressure applying mtA terminal 5.

a collector connected to the commonly connected emitter;
A drive current regulating transistor Qs whose emitter is connected to the voltage source 2 via a resistor R3, whose pace is a constant voltage application terminal 6, whose cathode is connected to the reference voltage application terminal 7 VC, and whose anode is connected to the base VC of the input transistor QI. fc clamp diode D. It takes out the logic output from the collector of the input transistor QI,
On the other hand, it is a logic circuit that extracts an affirmative logic chip from the collectors of reference transistors Q and n.

In this logic circuit, the potentials of reference voltage application terminals 5 and 7 are respectively *VS-Vt, and the base-emitter forward voltages of input transistors Q, I and reference transistor QB are respectively VFI.

Vr2 and the forward voltage between the anode and cathode of the clamp diode DC 'f-Vr3, the collector potential change of the drive current regulating transistor Qs when the input No. 111 changes significantly from the low level VIL to the tube level VIH. △■o is approximated by aVc (v, +
vra-Vpl)-(V5-Vr2)...
...... (4) "7+vF3"'V5"(Vr2"Fl)...
...... (5) It becomes.

'1, this collector potential change △Vc is short poem 1H] (△
t), then the transient current if'i flowing through s Ccs, Cj(k, approximately where the value of %V5 is determined from the open plane of the logic circuit.

This ttc vs. shite, Vr, Vr3 tD#U4,i
It is possible to set any VC within the range where normal logic operation is possible. Therefore, s V y , VJ, ? 3
the value of.

・、W common theory J、! (To the extent that it is possible to create i fi, (
6) The formula is the minimum (llt VCN currency footing is,
Large input jJ narrow VC pair (even if 7, input transistor Q,
x lr 1ti+ High speed 1γl without Ao
l1J:I!・l・rJ's work has been carried out in the town Ml, and it may be 1,...S city I) '+Ii: fAυ
, Cjc of 4 constant transistor Q3 1m and 1i8
The voltage noise at the voltage application terminal 6 is also large 114
&'C can be reduced by one time... Figures 153 to 10 are respectively...
An example of the funeral 9 is a road map in the direction of Bocho. Figure 31 shows the second
The clamp diode Dck shown in the figure is replaced by the clamp diode Dck and the barrier diode shown in Figure 4.
゛, the clamp diode IJc in Figure 2, with all collectors connected to voltage source 2?・Electric type transistor (C
VC currency exchange j7, and the logical operation is as shown in Figure 2.
, 'iIt is exactly the same as Riichi Kawaji. FIG. 5 shows an example in which the invention is implemented in n multi-input logic circuits V, in which the entire NOR output is output from the output nWA child 3, and the output terminal 4
There is a logic circuit that extracts the OR output from the logic circuit.

tJr 6 shows an example in which the present invention is implemented in a multi-input logic circuit with VCn, similar to that shown in FIG. 'f' is a logic circuit.'4rJ7 diagram is
The input diode in Fig. 36 is directly converted into a xn k multi-emitter type transistor QIN, and the logic operation is exactly the same as the logic 1 in Fig. 4.

FIG. 8 shows input diode JJIi and Schottky barrier diode JJx in FIG. 2 with 1αJi; 41. '7t, and the logic operation is exactly the same as the logic circuit in the m2 diagram.

FIG. 9 shows the input diode 1. of FIG. lIiReverse conductivity type transistor QxVc whose collector is connected to voltage source 2
The logic operation is exactly the same as the logic circuit shown in FIG. FIG. 10 shows an example in which the present invention is applied to a vertically connected current switching type logic circuit, in which a logic circuit takes out a negative logic output from output terminal 3 and a logic output from output terminal 4. It is.

Regarding the second to ninth embodiments VC described above, the effects of the present invention are exactly the same as those of the first embodiment.

As mentioned above, it is possible to perform transformations of the gods within the scope of this invention, and the scope of this invention is r.
ri applies to all claims BL.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the entire conventional logic circuit. 2nd to 10th are circuit diagrams showing first to ninth embodiments of the logic circuit according to the VC of the present invention. QIs W, I 1~QXn# QRt Q”t QR
2# QS# Qct QIN...Transistor, Rx, l(, z, R3, 几r, Rx1~几Ir
l...Resistance, L)I, DI 1~DXN,
Da, Dc 1~1)cn...Diode, IN, IN1~INn...Input, No. 1 application terminal, 1.2...Voltage source, 3,4・・・・・・
Output terminal. 5.6, 7, 8, 9... Voltage application terminal. Kyo l Figure 3 Figure #S Figure 6 Figure #S Figure 6 Figure 7 Figure 8 Written procedure amendment (method) 59.0.15 Showa year Month Day 1, Incident (7) Displayed in 1988* Wf Application No. 4547
9 No. 2, Title of the invention Logic circuit 3, Relationship to the amended person case Applicant 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative Tadahiro Sekimoto 108 Minato-ku, Tokyo 37-8 Shiba 5-chome Sumitomo Sanda Building 1 Hondenki Co., Ltd. (6591) Patent Attorney Susumu Uchihara Telephone: Tokyo (03) 456-3111 (main representative) (Contact information: NEC Corporation Patent Department) 5 Supplementary + EJ Date of order: July 31, 1980 B) 6 ``Brief explanation of drawings'' of the specification subject to amendment 7 Contents of amendment + 1) Page 13, line 7 of the specification “The 2nd to 10th are
" will be corrected to "Figures 2 to 10 are." Agent Patent Attorney Susumu Uchihara゛-゛-9-1

Claims (1)

[Claims] The cathode is an input signal application terminal, and the anode is IIt
Silk 1 connected to the first voltage source with the resistor closed (:
the base is the anode vC of the first rectifying element;
The collector is connected directly or through a resistor to the front 11-
1. A first transistor connected to the first 1u, Shobara rC, and an emitter of the first transistor tC.
When commonly connected, the constant current source 1-1 is connected to the second voltage source VC, and the collector is directly connected to the 1-1 resistor t.
・Through the above d! 1 voltage source, and the base is connected to the first voltage source.
a second transistor whose cathode is connected to the reference voltage application terminal VC, and whose cathode is connected to the second reference voltage application terminal VC;
The anode was connected to the base of the first transistor to VC. The collector potential change of the first or second transistor is taken out as a total output, and in the logic circuit, the second rectifying element clamps the voltage with respect to the input signal voltage VC. A logic circuit characterized by having the ability.