JPH01213026A - Logic circuit - Google Patents

Abstract

PURPOSE:To reduce a consumption current and to shorten a delay time by adding a switching current and flow it through a transistor when all the input terminals of a logic circuit are in an open condition. CONSTITUTION:When all input terminals I1, I2 and I3 are in an open condition, all input transistors(TR) Q1-Q3 are non-continuity. The electric potential of a point 1 emitter-common-connected becomes a floating condition, and a Q5 for difference goes to non-continuity. Then, a switching current supplied by a current source CS flows through an added TRQ4' for referring. a emitter follower current flows in a TRQ6 and a TRQ4 for referring. Then, the corrector electric potential of the input transistor lowers from a VCC electric potential for the voltage lowering at load resistance R1, and the corrector of the TRQ5 becomes about the VCC. Consequently, an output terminal O1 becomes an 'L', and an output terminal O2 goes to an 'H' by the base electric potential of the TRQ6 and a Q7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to high-speed logic circuits, and particularly to improvements in emitter-coupled logic circuits that improve speed performance and reduce power consumption.

[Conventional technology]

Figure 2 is a circuit diagram showing a conventional emitter-coupled logic circuit that improves speed performance and reduces power consumption.
2 illustrates an emitter-coupled logic circuit with a manually configured OR output and a NOR output.

In the same figure, Q1 to Q3 are input transistors whose bases are connected to the input terminals Q1 to Q3, respectively, and O4 has two collectors whose base is connected to the reference potential VBm and one collector is connected to the input transistors Q1 to Q3. A reference transistor O5 has two collectors, and its base is connected to the commonly connected emitters of the input transistors Q1 to Q3, and together with the reference transistor Q4, a differential amplification type switching circuit is formed. The constituent differential transistors, R1 are the first load resistors commonly connected to the collectors of the input transistors Ql-Q3, R2 are the second load resistors connected to one collector of the transistor Q5, and O8 are the reference transistors Q4 and A current source for supplying switching current and emitter follower current to which the emitters of the differential transistor Q5 are commonly connected, and the bases of O6 and O7 are connected to the collectors of the input transistors Q1 to Q3 and one collector of the transistor Q5, respectively. The emitter of the first output transistor Q6 and the other collector of the reference transistor Q4 are OR transistors.
The emitter of the second output transistor Q7 and the other collector of the differential transistor Q5 are connected to the output terminal O1.
They are respectively connected to the OR output terminal o2.

Note that "QC is the first power supply potential on the collector side, V.

indicates the second power supply potential on the emitter side.

Next, the operation of the logic circuit configured as described above will be explained.

First, input terminals II, I2. When the input potentials Vin applied to I3 are all at the logic level Vt, the potential at point 1, where the emitters of the input transistors Q1 to Q3 are commonly connected, is equal to the forward emitter-to-emitter voltage Vb of the input transistors.
The potential becomes Vt-Vbe, which is lowered by e. This is based on the pace potential and NAF of the differential transistor Q5, and the reference potential B1 applied to the base of the reference transistor Q4.The transistors Q1 to Q3 and the reference transistor Q4 are in a conductive state, and the transistor Q5 is in a non-conductive state. Become. Therefore, the collector potentials of the input transistors Q1 to Q3 are lowered from the VCC potential by the voltage drop across the load resistor R1, and the collector potential of the differential transistor Q5 becomes approximately the VCC potential. Therefore, according to the base potential of the output transistor Q6 and O7, the output terminal 01 is at the low logic level Vt, and the output terminal 0
2 becomes the high logic level vh.

On the other hand, input terminals II, I2. When the input potential Vin applied to at least one input terminal of I3 becomes a high logic level vh, the potential at point 1 becomes a potential vh - vbθ which is lower than vh by the pace-emitter forward voltage Vbe of the input transistor. Otherwise, the input transistors Q1 to Q3 and the reference transistor Q4 are in a non-conductive state, and the transistor Q5 is in a conductive state.

Therefore, the collector potentials of the input transistors Q1 to Q3 are approximately equal to the VCC potential, and the collector potential of the differential transistor Q5 is lower than the VCC potential by the voltage drop across the load resistor R2. Therefore, according to the base potentials of the output limiter follower transistors Q6 and O7, the output terminal 01 becomes a high logic level h, and the output terminal 02 becomes a low logic level Vt. From the above logic operation, 01 is the OR output terminal, and 02 is,
It becomes a NOR output terminal.

Reference transistor Q4 and differential transistor Q5
In addition to the logic operation, it also controls the current of the emitter follower transistor as shown below. That is, the input potential Vi
When all n are at the negative logic level Vt, almost no current flows through the emitter follower transistor QW having a NOR output (which is at this current logic level vh) because the differential transistor Q5 is in a non-conducting state, and the OR output ( At this time, current flows through the emitter follower transistor Q6, which has a low logic level (Vt), through the reference transistor Q4e. Further, when at least one of the input potentials Vin is at a high logic level vh, an emitter follower transistor Q has a NOR output (low logic level Vt at this time).
Current flows through the differential transistor Q5, which is in a conductive state, and almost all current flows through the emitter follower transistor Q6, which has an OR output (high logic level Vh at this time), since the reference transistor Q4 is in a non-conductive state. do not have. In other words, the circuit current can be reduced by allowing current to flow only to the emitter follower transistor that outputs the low logic level Vt.

Furthermore, in the above logic circuit, when the input potential Vin transitions from the low logic level Vt to the high logic level vh, the reference transistor Q4 becomes non-conductive, so the input transistors Q1 to Q3 also become non-conductive. Since the current supplied from the cannimitter follower transistor Q6 flows into the load capacitance added to the output terminal 01, the 19 o'clock delay time on the OR output is improved. At this time, the differential transistor Q5 becomes conductive, and the output terminal 0
Since the charge accumulated in the load capacitance loaded on the transistor Q2 is directly extracted through the differential transistor Q5, the NOR
The delay time when the output falls is improved.

On the other hand, when the input potential Vin transitions from the high logic level vh to the low logic level Vt, the reference transistor Q4 and input transistors Q1 to Q3 become conductive, the differential transistor Q5 becomes non-conductive, and the OR output rises. The delay time at the time of falling and at the time of rising of the NOR output is improved.

Furthermore, as is clear from the above description of the operation, in the conventional logic circuit, the base potential and collector potential of the input transistor change in phase, so it is possible to eliminate the increase in capacitance due to the Miller effect.

[Problem to be solved by the invention]

The above operation description assumes that a high logic level or a low logic level Vt is always given to the input terminal, but in the actual use state of the logic circuit, the power supply (Vcc * 'V++
) is applied and all input terminals are open. In the basic emitter-coupled logic circuit (not shown), opening all input terminals is equivalent to applying a low logic level Vt, which is hD, the OR output outputs a low logic level Vt, and the NOR output outputs a high logic level vh. However, the above logic circuit has the following drawbacks.

In Fig. 2, if the input terminals Q1 to Q3 are all open, the input transistors Q1 to Q3 are all non-conductive. Q5 becomes non-conductive. Therefore, the current continued to be supplied by current source C8K is
Output transistor Q6 and reference transistor Q4
It will flow through. At this time, the potential of the output terminal 02 becomes a high logic level 9 (because Q5 is non-conductive). −
The potential of the output terminal 01 is increased by the voltage drop across the first load resistor R1 due to the base current of the output transistor Q6 and the increase in Vbe of the output transistor Q6 due to the flow of all the current from the current source aS. Although the level is lower, it can be regarded as a high logic level vh. That is, when all the input terminals are in an open state, both outputs 01 and 02 are at a high logic level vh, and the logic operation is different from that of the basic emitter-coupled logic circuit.

The present invention has been made to solve these disadvantages, and aims to provide a logic circuit that can realize the same logic operation as a basic emitter-coupled logic circuit without sacrificing the advantages of the conventional logic circuit.

[Failure to solve the problem]

In the logic circuit according to the present invention, a reference potential is applied to the base, the collector is connected to the first power source together with the collectors of the input transistor group via the first load resistor, and the emitter is connected to the current source together with the emitter of the reference transistor. A transistor connected to the second power supply via the conventional circuit is newly added to the conventional circuit.

[Effect]

In this invention, even if all the input terminals of the logic circuit are open, the switching current can pass through the newly added transistor, thereby realizing the same logic operation as the basic circuit of emitter-coupled logic.

[Embodiments of the invention]

FIG. 1 is a circuit diagram showing an embodiment of a logic circuit according to the present invention, and particularly shows an emitter-coupled logic circuit having three circuits and having an OR output and a NOR output.

In the figure, Q1 to Q3 are input transistors whose bases are connected to input terminals 11 to 3, respectively, and O4 has two collectors, whose base is connected to a reference level VB11 and one collector is connected to input transistors Q1 to Q3. A first reference transistor Q4' connected to the commonly connected emitters of Q3 is connected to the reference potential BB, its collector is connected to the collectors of the input transistors Q1 to Q3, and its emitter is connected to the first reference transistor Q4'. A second reference transistor O5 connected to the emitter of Q4 has two collectors and a base connected to the commonly connected emitters of the input transistors Q1 to Q3.
4. A differential transistor that constitutes a differential amplification type switching circuit together with Q4', R1 is an input transistor Q1
~ Q3 and a first load resistor commonly connected to the collectors of the second reference transistor Q4', R2 is a second load resistor connected to one collector of the differential transistor Q5, O8 is ml, the second load resistor is The emitters of the reference transistors Q4, Q4' and the differential transistor Q5 are connected in common to current sources for supplying switching current and emitter follower current, and O6 and O7 have their bases connected to the collectors and differential transistors of the input transistors Q1 to Q3, respectively. The emitter of the first output transistor Q6 and the other collector of the first reference transistor Q4 are The emitter of the second output transistor Q7 and the other collector of the differential transistor Q5 are connected to the OR output terminal 01, and the NOR output terminal 02, respectively.

That is, in this embodiment, a second reference transistor Q4' is added to the conventional circuit shown in FIG.

Next, the operation of the logic circuit configured as described above will be explained.

First, input terminal 1, input terminal 2. Input potential T applied to I3
When in is all at the low logic level vt, the potential at point 1 where the emitters of input transistors Q1 to Q3 are commonly connected is:
The potential Vl-Vbe is lowered by the base-emitter forward voltage Vbe of the input transistors Q1 to Q3. This becomes the base potential of the differential transistor Q5, and by appropriately setting the reference potential VBB applied to the bases of the first and second reference transistors Q4eQ4 (in this case vh+vl-Vbe), the input transistors Ql to Q3 and the The first and second differential transistors A and l become conductive, and the differential transistor Q
6 becomes non-conductive. At this time, the switching current supplied by the current source aS is the input transistor Q1-c.
The collector potential of the differential transistor Q5 is lowered from the Vcc potential by the voltage drop of the x-th and second reference strands, and the collector potential of the differential transistor Q5 becomes approximately the V'cc potential. Accordingly, according to the base potential of the output limiter 7 oror transistors Q6 and Q), the output terminal 01 becomes a low logic level V/, and the output terminal 02 becomes a high logic level vh.

On the other hand, at least among the input terminals lit1g and 13
When the input potential Vin applied to the 51 input terminals reaches a high logic level vh, the potential at point 1 changes from vh to 1 unidirectional voltage Vb between the bases and emitters of input transistors Q1 to Q3.
e decreases to the potential Vh-'Vbe, and the input transistor N1 and the second reference transistor Q4.
Q, 4' are in a non-conducting state, and the differential transistor Q5 is in a conducting state. Therefore, the collector potential of the input transistors Q1 to Q3 becomes approximately the Vcc potential, and the collector potential of the differential transistor Q5 decreases from the Vcc potential by the voltage drop across the load resistor R2.

Therefore, output limiter follower transistors Q6 and O7
According to the base potential of the output terminal 01 is at a high logic level vh,
Output terminal 02 is at low logic level 'VI! becomes.

That is, the fact that 01 is an OR output terminal and O2 is a NOR output terminal is the same as in the conventional circuit shown in FIG.

In addition, the circuit current is reduced by allowing current to flow only to the emitter follower transistor that outputs the low logic level Vt by the operation of the first reference transistor Q4 and the differential transistor Q5, which remains the same as in the conventional circuit. .

Here, the input terminal I2. Consider the case where I3 is all open. Since the input transistors Q1 to Q3 are not supplied with pace current, they all become non-conductive, and the potential at point 1, where the emitters are commonly connected, becomes floating. Therefore, differential transistor Q5 becomes non-conductive. At this time, the switching current continued to be supplied by the current source aS is transferred to the newly provided second reference transistor Q4/
The emitter follower current will flow through the output transistor Q6 and the first reference transistor Q4. Therefore, the collector potential of the input transistor is separated from the VCC potential by the voltage drop across the load resistor R1, and the collector potential of the differential transistor Q5 is approximately VCC.
It becomes electric potential. Accordingly, the output terminal 01 becomes the low logic level Vt and the output terminal 02 becomes the high logic level vh according to the base potentials of the capacitor follower transistors Q6 and Q7. The above logic state is equivalent to the case where the potentials of the input terminals 1 to I3 are all at the low logic level Vt, and the logic operation is the same as that of the basic circuit of the emitter coupled logic. ′
Further, in the logic circuit of the above embodiment, the input potential Vin
transitions from the low logic level Vt to the high logic level vh, the first and second reference transistors Q4
．． Since Q4' becomes non-conductive, the input transistor Q1
~Q3 also becomes non-conductive, and the current supplied from the crabmitter follower transistor Q6 flows into the load capacitance added to the output terminal 01, so the 19:00 delay time on the OR output is improved as in the conventional circuit. . At this time, the differential transistor Q5 is not in a conductive state, and the charge accumulated in the load capacitance loaded on the output terminal 02 is directly extracted through the differential transistor Q5, improving the delay time when the NOR output falls at 9. be done. On the other hand, when the input potential Vin transitions from the high logic level vh to the low logic level Vt, the reference transistor Q4 and the input transistor become conductive, the differential transistor Q5 becomes non-conductive, and the falling edge of the OR output This improves the delay time at rise time and the rise time of the NOR output. The above-mentioned improvement effect and the effect of suppressing the increase in capacity due to the Miller effect are the same as in the conventional circuit example.

〔Effect of the invention〕

As described above, according to the emitter-coupled logic circuit according to the present invention, the second reference transistor is newly provided and the circuit configuration is such that the switching current flows through this transistor when all the input terminals are open.
This has the effect of obtaining the same logic operation as the basic circuit of emitter-coupled logic without sacrificing the advantages of conventional circuits, such as reducing power consumption and improving delay time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional logic circuit. In the figure, Ql, Q2. Q3 is the input transistor, I
I, I2. I3 is an input terminal, Q4 is a first reference transistor, Q4' is a second reference transistor, Q5 is a differential transistor, Q6 is a first output transistor, Q7 is a second output transistor, and R1 is a first load. resistance, R2 is the second load resistance, as is the current source, VB
B is the reference voltage, VCC is the first power supply, Vlm is the second power supply, 01 is the first output terminal, and 02 is the second output terminal. Show O

Claims (1)

[Claims] (1) A group of input transistors whose respective bases are connected to an input terminal, whose commonly connected collectors are connected to a first power supply via a first load resistor, and whose respective emitters are commonly connected; a first output transistor connected to a first power source, a base connected to the commonly connected collector of the input transistor, and a first output terminal drawn out from the emitter; a collector connected to the first power source; a second output transistor having a base connected to the first power supply through a second load resistor and a second output terminal drawn out from the emitter; and two collectors, one of which is connected to the first power supply. a first reference transistor whose collector is connected to the commonly connected emitter of the input transistor, whose collector is connected to the first output terminal, whose base is supplied with a reference potential, and whose emitter is connected to a second power supply via a current source; and has two collectors, one of which is the second collector.
The other collector is connected to the first power supply through a load resistor, the other collector is connected to the second output terminal, the base is connected to the commonly connected emitter of the input transistor group, and the emitter is connected to the common connection emitter of the first reference transistor. In a circuit having a differential transistor connected to an emitter, the reference potential is supplied to the base, and the emitter is connected to the first differential transistor.
A logic circuit characterized in that the emitter of the reference transistor is provided with a second reference transistor whose collector is connected to the commonly connected collector of the input transistor.