JPS60138792A - Memory device - Google Patents

Abstract

PURPOSE:To improve the operating speed of a system using a memory by comparing an input/output of a write/read data amplifier of a memory cell so as to generate a write/read end signal to the memory cell thereby eliminating unnecessary wait period. CONSTITUTION:A write input data via a data control circuit 14 is latched to a control circuit 17, amplified by a sense amplifier 13, written in the memory cell 11 and H or L is identified clearly by a comparator 15 to which a reference level is set. Then the output of the comparator 15 and the circuit 17 is compared by a comparator 16 and when they are coincident, a write end signal is outputted and a CPU is started immediately to this signal. A read end signal is outputted similarly. Thus, it is not necessary to provide an unnecessary prescribed period of wait period to the CPU, and the operating speed of the system using the memory cell is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory device that improves the operating speed of a memory-using system by generating data write and read end signals.

[Technical background of the invention and its problems]

As is well known, in a control system using a microcomputer, for example, data transfer between the central processing unit (hereinafter referred to as CPU) of the microcomputer and a memory device is performed using a synchronous bus method.
The timing is as shown in FIG. 11Cyr. That is, address data A is generated at the timing shown in the figure with respect to the synchronous clock signal ψ, and at this time, the address data A is
The write request signal (hereinafter referred to as W) is H (high)
If the level (read request state), data D is read out in synchronization with ψ. In addition, if the W signal is at L (low) level (waiting request state), data D is synchronized with ψ.
is written.

On the other hand, FIG. 2 shows the timing relationship of the asynchronous bus system. In this case, since the access speed of the memory device is slow compared to the operating speed of the CPU, the CPU generates an operation wait signal WAIT (L level) and provides a wait cycle Tw for ψ. ing.

This wait period is usually set to a length that is the maximum value of the access time specified for the memory device plus an extra margin. This margin means, for example, that the access time of a memory device changes due to fluctuations in power supply voltage and temperature, variations in the characteristics of the conductor resistors that make up the memory cell, etc. It is something that

By the way, in practice, memory devices often perform read and write operations in a time shorter than the standard access time. and (even if reading is possible, the CPU mechanically outputs the wait signal WA).
Since IT occurs for a predetermined period of time, the period shown by the dotted line in FIG. The purpose of this invention is to provide an extremely good memory device that eliminates unnecessary wait periods and improves the operating speed of the entire memory usage control system. The present invention provides an amplification system which is interposed in the input/output line for data to and from a memory cell, amplifies input data from the outside during storage and guides it to the memory cell, and amplifies output data from the memory cell during readout and leads it to the outside. and comparing means for comparing the human output data of the amplifying means and generating a data vl write and read end signal to the memory cell.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 3, 1 is, for example, MO8I-
This is a memory cell constructed using a transistor or the like, and is accessed based on address data supplied to an address data line (not shown). A data input/output line 12 of this memory cell 11 is connected to a data control circuit 14 via a sense amplifier J3.

Therefore, the data control circuits 14B and E? ,A
When a commitment request is made by the I+r signal, input data is supplied to the memory cell 11 via the sense amplifier 13, and when a commitment request is made by the p signal, input data is supplied from the memory cell 1 to the sense amplifier 11. 3 and outputs the data obtained through 3 to the outside. Furthermore, the sense amplifier 13 operates to amplify the output data of the data control circuit 14 and guide it to the memory cell J1, and also to amplify the output data of the memory cell 11 and guide it to the data control circuit J4.

Here, the connection point between the memory cell 11 and the sense amplifier 13 is connected to one input terminal of the comparator 15.

Further, a reference level which is approximately the middle level between the Hl/bell and L level of the data stored in the memory cell J is applied to the other input terminal of the comparator J5. The output terminal of the comparator 15 is connected to one input terminal of another comparator 16. In addition, the above sense amplifier 1
The connection point between the data control circuit 3 and the data control circuit 4 is connected to the other input terminal of the comparator 16 via the control circuit 17. And the control circuit 17
latches the output data from the data control circuit 14 when a write request is made by the R/W code, and
When a read request is made by the 7W signal, the output data from the sense amplifier 13 is directly output to the comparator 16.

Here, the memory device described in this example is R
When the /W signal is supplied and data writing and reading are requested, as shown in FIG. If the data is at H level, the state of the trench is maintained as it is, and if it is at L level, it is inverted to L level.

The operation of the above configuration will be explained below.

First, when input is requested from the R/W signal eζ, the data output line 12 is forcibly set to HI/bevel as shown in FIG. 4, and then supplied to the data control circuit 14. The input data is output to the data output line 12. Then, at time T in FIG. 4, when one time elapses from when the data input/output line J2 is set to the forced KH level until the state is released, the sense amplifier 13 is put into the operating state, and the input take becomes the sense amplifier 13. 3 and written into memory cell J.

At this time, the data output from the data control circuit 4 to the sense amplifier 13 is applied to the control circuit 17V.
C is latched and output to the comparator 16. Further, after the time T, the data amplified by the sense amplifier J3 is supplied to a comparator J5 and compared with a reference level, and when it is higher than the reference level, it is output as an H level, and when it is lower than the reference level, it is output as an L level. That is, the comparator 15 has the function of clearly determining whether the data written into the memory cell J1 is at the H level or the L level.

Each output data from the comparator 15 and the control circuit NOR is compared by the comparator 16, and when both outputs match, a termination signal is output to the CPU. That is, in this case, the output data from the sense amplifier 13 is directly supplied to the memory cell J, so the output take of the sense amplifier 7-13 is 1 to the memory cell 11.
, can be considered as imported data. For this reason,
Senua:/F1. The output data from wo is compared with the reference level by the comparator 15, and the data clearly determined as H level or L level is compared with the input data output from the data control circuit 4 to the sense amplifier 13. The fact that they match when compared with each other means that there is no problem in determining that the temporary input data to the memory cell IIVc has been completed without making any corrections. Therefore, by outputting the completion signal from the comparator J6 to the CPU, the CPU determines that writing to the memory cell 1lkc has been completed, and can promptly shift to the next control operation.

Furthermore, when reading is requested by the R/W signal, the data input/output line J2 is forcibly set to H level as shown in FIG. 4, and then data is output from memory cell 1 to the data input/output line J2. be done. Then, as described above, at time T, the sense amplifier 13 is brought into operation, and the output data from the memory cell 11 is transferred to the sense amplifier 1.
C through the data control circuit No. 4.
Output to PU.

At this time, the output data from the memory cell J7 is supplied to the comparator 16 via the comparator 15, and the sense amplifier 13
The output data is sent to the comparator 1 via the control circuit 17.
6, and when both output data match, a termination signal is generated.

Since the output data from memory cell 1 and the output data from sense amplifier 13 match, it can be determined that data has been read from memory cell 1, and therefore comparator 16 is terminated. By outputting the signal 'kcPU, the CPU determines that data has been read from memory cell 1, and can quickly perform operations such as inputting data from the data bus.

Therefore, according to the configuration of the above embodiment, the CPU
In this case, it is possible to perform the next process after determining that the writing and reading of the take for memory cell 1 is completed based on the end signal from the memory device, so a wait time period of a certain period is set as in the conventional method. Compared to
The operating speed of the control system can be fully improved. Further, during reading, the output data from the memory cell 1 may be directly guided to the comparator 16 without operating the comparison signal 5 in response to the R/W signal.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and may be implemented with other glazes without departing from the spirit of the invention.

〔Effect of the invention〕

Therefore, as described in detail above, according to the present invention, it is possible to provide an extremely good memory device that eliminates unnecessary wait periods and improves the operating speed of the entire memory usage control system.

[Brief explanation of drawings]

1 and 2 are timing diagrams for explaining the operation of a conventional memory device, respectively. FIG. 3 is a block configuration diagram showing an embodiment of the memory device according to the present invention, and FIG. 4 is the same embodiment. FIG. 1. Memory cell, 12. Data input/output line, J3. Sense amplifier, 14. Data control circuit, 15.16. Comparator, 17. Control circuit.

Claims (1)

[Claims] 1. For data input/output lines to/from memory cells. - an amplifying means for amplifying input data from the outside and guiding it to the memory cell during reading, and for amplifying output data from the memory cell and leading it to the outside during reading; and input/output data of this amplifying means. 1. A memory device comprising: comparing means for comparing data and generating a data omitting and reading end signal for the memory cell.