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JPS54123841A - Semiconductor integrated memory element - Google Patents

Semiconductor integrated memory element

Info

Publication number
JPS54123841A
JPS54123841A JP3059778A JP3059778A JPS54123841A JP S54123841 A JPS54123841 A JP S54123841A JP 3059778 A JP3059778 A JP 3059778A JP 3059778 A JP3059778 A JP 3059778A JP S54123841 A JPS54123841 A JP S54123841A
Authority
JP
Japan
Prior art keywords
circuit
memory
memory operation
operation end
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3059778A
Other languages
Japanese (ja)
Other versions
JPS579153B2 (en
Inventor
Shigeru Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP3059778A priority Critical patent/JPS54123841A/en
Publication of JPS54123841A publication Critical patent/JPS54123841A/en
Publication of JPS579153B2 publication Critical patent/JPS579153B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To enable to most efficiently use the speed performance and to simplify the timing of the memory unit, by outputting the memory operation end signal and enabling easily to discriminate the end of the memory operation of the memory element from external easily. CONSTITUTION:The memory operation end output signal generating circuit 27 is provided. The circuit 27 is controlled with the internal control signal and the internal timing generating circuit 8, and the memory operation end output signals EO1...EOi...EOs are outputted at the time point of each memory operation end for the memory element. The address signals A1...Ai...An in n-bits enter the address signal input circuit 1, are decoded 2 and given to the memory cell arrangement 3, and the write-in data signals DI1...DIi...DIm in m-bit are written in the arrangement 3 via the readout and write-in data selection circuit 4 and the write-in data input circuit 5, and the memory information is read out to the readout data output circuit 7 via the circuit 4.
JP3059778A 1978-03-17 1978-03-17 Semiconductor integrated memory element Granted JPS54123841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3059778A JPS54123841A (en) 1978-03-17 1978-03-17 Semiconductor integrated memory element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3059778A JPS54123841A (en) 1978-03-17 1978-03-17 Semiconductor integrated memory element

Publications (2)

Publication Number Publication Date
JPS54123841A true JPS54123841A (en) 1979-09-26
JPS579153B2 JPS579153B2 (en) 1982-02-19

Family

ID=12308268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3059778A Granted JPS54123841A (en) 1978-03-17 1978-03-17 Semiconductor integrated memory element

Country Status (1)

Country Link
JP (1) JPS54123841A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60138792A (en) * 1983-12-27 1985-07-23 Toshiba Corp Memory device
US6188638B1 (en) * 1998-08-27 2001-02-13 Siemens Aktiengesellschaft Integrated semiconductor memory with control device for clock-synchronous writing and reading

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60138792A (en) * 1983-12-27 1985-07-23 Toshiba Corp Memory device
US6188638B1 (en) * 1998-08-27 2001-02-13 Siemens Aktiengesellschaft Integrated semiconductor memory with control device for clock-synchronous writing and reading

Also Published As

Publication number Publication date
JPS579153B2 (en) 1982-02-19

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