JPS60113971A - Thin-film field-effect type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To stabilize OFF characteristics by forming a semiconductor film having large Fermi level energy to the surface positioned on the side reverse to the gate electrode of a semiconductor film forming a channel section. CONSTITUTION:A nonsingle crystal semiconductor 11, which differs from a layer 4 having the following properties and mainly comprises Si, is formed to the surface positioned on the side reverse to the surface being in contact with a gate insulating layer 3 in a region as a channel of the semiconductor layer 4. The properties are that Fermi level energy DELTAEF=EC-Ef measured from conduction band width EC is larger than the layer 4 shaping the channel in a semiconductor thin-film FET. Accordingly, stable characteristics can be displayed particularly under an OFF state even when there are gas adsorption, difference in the manufacture of an insulating film 8 in a process for shielding beams and charges by the floating potential of an optical shielding metal 9 on the free space side.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a thin film field effect transistor and a method for manufacturing the same, and particularly relates to a thin film field effect transistor and a method for manufacturing the same.
The present invention relates to a semiconductor thin film field effect transistor (hereinafter referred to as TPT) whose main component is a group Ⅰ element such as a non-single crystal silicon or silicon compound semiconductor film such as ), and a method for manufacturing the same.

Conventional Structures and Problems They are fabricated at relatively low temperatures below 600°C by plasma deposition, sputtering, or thermal CV-D, and imperfections in atomic bonding pairs are compensated for by hydrogen, fluorine, etc. Non-single-crystalline semiconductor thin films mainly composed of group II elements, typified by amorphous silicon, exhibit weak n-type or intrinsic electronic conductivity and have an electron mobility of 0.1 to 10 c++t/V sec. Since it has a large surface area and a high resistance compared to single crystal silicon or the like, a large ratio of on resistance to off resistance (ON-OFF ratio) can be obtained when TPT is used without forming a pml junction isolation. Therefore, these semiconductor TPTs are promising for application to switching arrays and the like that configure image display devices and the like by combining with liquid crystals, and configure image sensors by combining with light-receiving elements.

The TPT using an a-SiH film will be mainly described below.

FIGS. 1(a) and 1(b) show typical structural cross-sectional views of an inverted staggered TPT using a conventionally used hydrogenated amorphous silicon (a-8i:H) semiconductor.

Figure 1(a) shows the configuration of a conventionally used TPT.

(b) will be used to explain the manufacturing process. First, a metal such as Cr is deposited on a substrate 1 such as glass and etched, leaving a portion to become the gate electrode 2. Next, a silicon nitride film 3 (hereinafter referred to as SiN) of 0.1-0.
Ei μm, a-8i: H film 4 is 0.1-0.5 μm, n
The a-Si:H films 5a and 5b doped with
Approximately 1,000 pieces are deposited continuously. Next, the part to be left as TPT is covered with resist, and the remaining part n+a-3i
:H, a-8i: Remove the H film with esotinog. Then Aλ
The source and drains ti6a and 6b are patterned 4.

Furthermore, using the AJ2 electrodes 6a and 6b as a mask, the n+a-5i:H partial region 7 existing between the two electrodes is etched, thereby completing the TFT having the structure shown in FIG. 1(d).

In the structure of FIG. 1(a), the surface of the region 7 of the a-3i:H film 4 located on the opposite side to the gate insulating film SiN3 is
It is a free surface, and its electronic state is very sensitively affected by the adsorption of gases such as water and NH3, and by the coating of alignment films when applied to liquid crystal panels.

Therefore, in order to exclude the influence of external light on the a-8i:HTFT, the TPT having the structure shown in FIG. Transfer the Jahei money R9 to the TPT channel section (
Figure 1 of the TPT (outside the circle indicated by
There is b). In this case as well, due to the deposition method of the insulating film 8 and the floating potential of the photoreceptive metal 9, the
The surface indicated by changes sensitively.

The sensitive changes are shown in Figures 1 (a) and (b) (D).
This will be explained using FIGS. 2(a), 2(b), and 2(C), which are band structure diagrams of a-3i: HTFT in the cross section of . Figure 2 (a), (b).

In (C), the designation of numbers is the same as in FIG. 1, 2 is the gate electrode part, 3 is the gate insulating layer, and 4 is the semiconductor layer part, and the band structure is shown, E c , E y .

EF indicates conduction band edge energy, valence band edge energy, and Fermi level energy, respectively.

Also, Δ1. Δ2 is the Debye length. In the initial state in which no voltage is applied to the gate electrode 2, the semiconductor layer 4 is shown in FIG. 2(a).
Assume that the conduction band edge of is Nrasoto.

Next, when a gate voltage Va is applied to the gate electrode 2, the conduction band edge Ec on the interface side with the gate insulating layer 3 of the semiconductor layer 4 is about the depth of the Debye length Δ1, as shown in FIG. 2(b). It bends downward in the region of , and the TPT becomes ON. If there is no electric field from the free space 10 side, Fig. 2(a),
As shown in (b), the conduction band edge Ec of the semiconductor layer 4 on the free space 10 side is flat. However, if there is normally no passivation film on the free space 10 side, gases having electronegativity different from that of the semiconductor layer will be adsorbed, and a charge Q will be generated on the surface.

Even if an insulator is added to the semiconductor layer for passivation or a metal for light shielding, a charge Q will be generated at the interface with the semiconductor layer depending on the manufacturing method, film quality, and floating potential of the metal for light shielding. cause

Due to this charge Q (if positive), the free space 1 of the semiconductor layer 4
The o-side conduction band edge Ec bends downward within a depth range of approximately Debye length Δ2, and the amount of bending is approximately Δ■ at the interface between semiconductor layer 4 and free space 10. Δ2 and ΔV are expressed as follows.

ΔV=2.44. x1o15-Q/J ,,-++・+
+・+(1)Δ=2.5csx1o'10− ・・−
(2) However, ρ is the in-gear level prime degree (Crn-5·eV-1) near the Fermi level of the semiconductor layer 4. Q is the amount of electric charge [coulomb/crt: ]. As a result,
Channeling due to band bending also occurs on the free space 10 side of the semiconductor layer 4 and is added to the drain current of the TPT. Therefore, the O of the TPT characteristics
Even in the FF state, that is, when no gate voltage G is applied to the gate electrode 2, a train current due to electrons flows along the channel on the free space 10 side of the semiconductor layer 4 generated by the positive charge Q, and the TET The OFF current increases,
As a result, the ON-OFF ratio (ratio of ON current to OFF current) of the TPT decreases. Due to this phenomenon, the conventional n
(Mold Enhancement) TPT's characteristics varied greatly depending on the manufacturing method and environment, and it lacked reproducibility and reliability.

For the purposes of the invention, the present invention improves the drawbacks of conventional TPTs (particularly n-type enforcement TFTs) as described below, and improves the OFF of TPTs.
By stabilizing the F characteristic, T with excellent reproducibility and reliability
The purpose is to provide PT.

Structure of the Invention The structure of the present invention will be explained below with reference to FIGS.

The feature of the present invention is that a second non-single crystal semiconductor 11 mainly composed of silicon is provided at least in the core of the semiconductor layer 4, and has the following properties.

The property is that [- the Tschulmi level energy ΔEF-(EC-Ef) measured from the conduction band edge Ec is larger than the first semiconductor layer 4 formed by the TPT channel.

That's what it means.

The present invention t7) T F' T, FIG. 3(a), (
FIGS. 4 and 5 show band structure diagrams of the a-8i:HTFT in the section (IV) of b).

FIG. 4 shows an example having a homojunction of a non-doped a-3i:H layer 4 and an a-8t:H layer packed with valence electrons controlled to be more intrinsic or weakly p-type. That is, on the surface of the free space 10 side of the a-8t:H film layer 4, the Fermi level energy ΔEF2-EF-EC measured from the conduction band edge Ec is equal to the Fermi level energy ΔEF1 of the a-3i:H film (usually 0 .5-o, 5eV
) is larger (ΔEF2>ΔEF1) The semiconductor layer 11 is doped with a group II element such as boron, and is made of an intrinsic or weak p-p semiconductor layer 11.
A valence electron controlled a-3i:H film layer 1 is placed on the mold.

In this way, gas adsorption on the free space 10 side, differences in the manufacturing method of the insulating film (8 in FIG. 3) in the process of preventing light blocking, and charges generated due to the floating potential of the light blocking metal 9 can be avoided. Even if Q exists, the downward bending amount ΔV of the conduction band edge Ec on the free space 10 side surface of the semiconductor layer 11 due to the charge Q can be kept within the condition of ΔV(ΔEF2−ΔEF1, and this The electron current component due to band bending can be made so small that it hardly contributes to the inherent off-state current of the TPT.
PT exhibits a stable ON-OFF ratio characteristic in which the FF current is not influenced by the free space 1o side.

Figure 5 shows the a-3i:H film 4 and the energy gap Eg.
=EC-Ev is a-8i:H film (usually E9-1.6~1
．． 8) A case where a heterojunction with the larger second semiconductor layer 11 is provided. For example, carbon as the semiconductor layer 11,
An amorphous silicon compound semiconductor layer (SICx: 1-1 film SiOx:H film or SiNx:H film) containing oxygen or nitrogen in a large number to about 70 parts is used. In this way, the condition of ΔEF2>ΔEF1 is naturally satisfied, and the a-3i:HTF with stable 0N-OFF ratio characteristics as described above.
T is obtained. Also 5iCx:H.

By doping SiOx:H or SiNx:H with group III elements such as boron, ΔEF2 can be further increased, and ΔEF2 can be further increased.
■ It is easy to make the condition of ∆EF2 - ∆EF1 appear.

This means that due to the influence of the free space 10 side,
<The effect is large.

Furthermore, p-type a-3i:H film containing group II such as boron, and 5iC
x:H, SiOx:H, SiNx:H film, etc. (7J) 7
, /l/The gear state density ρ (CnIeV) near the Mi level energy EF is ρ of a-8t:H (approximately 1
015-10 cm eV) thicker (,10-10
crneV- level. Therefore, due to the influence of the charge Q on the free space 10 side shown in FIGS. 4 and 6, the electron conduction band edge Ec
The depth in the film thickness direction of bending (Debye length) Δ2
As is clear from equations (1) and (2), the bending amount Δ■ is 1/3 to 1/1 compared to the a-8i:H film, respectively.
a-3i which becomes small to about 0o and forms a channel
:H film 4(/i is hardly influenced by the free space 10 side.

DESCRIPTION OF EXAMPLES Hereinafter, examples of the present invention will be described in detail, including manufacturing methods.

[First Embodiment] FIGS. 6 and 7 show the manufacturing process of the TPT of the first embodiment and sectional views of essential parts.

First, chromium is deposited on a substrate 1 such as glass and etched, leaving only the part that will become the gate electrode 2 [FIG. 6(a)].
. Next, a silicon nitride film 3 with a thickness of 40% is formed by plasma CVD.
About 008, a-8i:H film 4 about 40Q08, n+
A doped a-3i:H film 6 is successively deposited by about 600 people under vacuum. Next, the portion to be left as TPT is covered with photoresist, and the remaining portion is coated with n+a −3i:H film 5a.
-5i: Etching and removing the H film 4 [Figure 6(b)]
.

Next, a multilayer metal of chromium and aluminum is deposited and patterned as source and drain electrodes 6a and 6b, and n+a-8i:H5 present between the two electrodes is removed by etching using the source and drain electrodes ea and eb as masks. n+a-8t:H film regions 5a, 5 for ohmic contact between the source and drain electrodes 6a, 6b and the a-8t:H film.
b [Fig. 6(C)]. Furthermore, o, 1 vol was added to the silane gas and methane gas mixed at a flow rate ratio of 70:30.
A p-type 5iCx:H film 11' of about 5008-10008% is deposited on the entire surface by plasma CVD with diborane of about 10% mixed therein (see Fig. 6).

Finally, polyimide is selectively deposited to form an insulating layer 8 of about 1 μm, and a light shielding plate 9 made of molybdenum metal or the like is formed on top of this to prevent external light from entering the channel portion of the TPT. 8 as a mask, the 5iCx layer 11' is selectively removed to form the semiconductor layer 11 shown in FIG. 3, and the TPT of the present invention shown in FIG. 6(e) is manufactured.

Δ”F2 of p-type 5iCx:H layer 11 in this example
is 1.4 eV, and in FIG. 5, ΔE - ΔEF1 is approximately 0.7 eV. Also, the gear level density ρ near the level energy of Fuenobe 2 is approximately 1018
on-3eV-", and the length Δ2; 260
It becomes eight. Therefore, if 500 layers of 5iCx:H layer 11' are deposited, the penetration of the electric field (TE length) due to external fixed charges will be sufficiently absorbed by 5iCx:H, and the TPT O
Does not deteriorate FF characteristics. Furthermore, the amount of charge NS (Q/ec
cn-21; e electron charge coulomb) is 1012(-
cm-2: ] (gate voltage 2O-30
Even if the amount of downward bending Δ■ of the bunt on the surface of 5iCx:H is about 0.4 eV, ΔV=
0.4eV (ΔEF2-ΔEF1-0.7e■ condition is satisfied, TP due to electron conduction due to band bending
Does not deteriorate the OFF% property of T.

FIG. 7 shows drain current (D) (A-gate voltage (GCV)) characteristics of the TPT of the present invention. Conventionally, the 5iCx of the present invention
: TPT light shielded without using the H layer 11 [Figure 7 (B)] is compared with TPT measured in a dry atmosphere before undergoing the light shielding process [Figure 7 (8)]. As a result of the drain current rising near vG-0 and the OFF current increasing, the 0N-OFF ratio deteriorates from 105 to 105.

On the other hand, in the TFT of the present invention [: Fig. 7(C)), TP
Gate threshold voltage of T■ Although T is slightly shifted to the negative side of the gate voltage, the ON-FF characteristics are 5 digits (10)
The above is maintained.

[Second Example] A second TET manufacturing example according to the present invention is shown in FIG. 8(a).
, (b) will be explained using the main part process sectional view. Figure 8 (
a) is TPT manufactured through the same process as before,
Formation of source and drain electrodes has been completed.

Next, using the source and drain electrodes as masks, at least one element among boron, carbon, nitrogen, and oxygen is implanted into the back surface of the semiconductor layer 4 by an ion implantation method into the channel portion of the TPT, thereby doping the region. This doped region is used as the semiconductor layer 11 to complete the TPT of the present invention (FIG. 9(b)).

[Third Embodiment] A third embodiment of the TPT manufacturing method of the present invention will be explained with reference to main part process sectional views in FIGS. 9(a) to 9(e). A substrate 1 on which a metal such as chromium is selectively deposited as a gate electrode 2.
[FIG. 9(a)], a thiosinated silicon film 3 and an a-3i:H film 4 are each formed with a thickness of 0.1 μm as a gate insulating film.
It is deposited to a thickness of about 0.4 μm using a plasma CVD device. Subsequently, SiC films 11' and 4 containing 1010 at of boron are formed.
a-9i:H film 15°n4-toped a-3 equivalent to
The i:H film 5 has a thickness of 100, 1000, and 50, respectively.
08 continuous deposits [Fig. 9(b) -' o first a-8i: H film 4, SiC film 11', second a
-3i:H film 16. Using the photoresist as a mask, the n+ doped a-3i:H film 5 is etched using a plasma etching device into which a mixed gas of CF4 gas and 02 gas is introduced to remove unnecessary portions and turn the film to form a SiC semiconductor film 11. Figure 9 (C)].

Metal such as aluminum is used as source and drain electrodes 6a, 6.
9(d)], the source and drain electrodes 6a and 6b are used as masks and a mixture of hydrofluoric acid, nitric acid, and water is used to remove the second layer existing between the drain electrodes.
a-3t: H film 15. By selectively removing the n+ doped a-3i:H film 5, the T shown in FIG.
PT is completed. 5a.

5b is the source, drain (7 electrodes 6a, 5b and a-3i: H
Ball blocking layers 15a, 15bij: They contribute to improving the ohmic contact with the film 4 and improve the hole blocking performance.

The first feature of this structure and manufacturing method is that the surface of the a-3t:H film 4 opposite to the gate electrode 2 is doped with boron, similar to other embodiments of the present invention. H(
x=o-0,7) By installing the membrane 11, it is isolated from subsequent processes and influences from the outside, and a stable TPT in an OFF state can be provided.

The second feature of this embodiment is that in the process of selectively removing the ohmic layer 5 and the blocking layer 15, the boron-doped 5iCx:H film 11' acts as an etching stopper, eliminating unnecessary a-3i:H etching. This means that there is no need to remove the film 4, there is no thinning of the a-3i:H film 4, and the thickness falls within the designed thickness of TPT.

In the above, a stacker type T having a gate insulating film on one side of a semiconductor thin film and source and train electrodes on the other side is used.
The present invention has been described in detail with respect to an inverted stagger type TPT having a structure in which a gate electrode is first formed on the substrate side as illustrated in FIGS. 3.6, 7, 9 and 10.11. The basis of the present invention is to embody the idea shown in the band diagrams in Figs. 4 and 5 in TPT, and to form a coplanar film with a gate insulating film, a source, and a pole about train 1 on one side of a semiconductor thin film. Of course, it also applies to types.

Effects of the Invention In the present invention, the Fermi level energy ΔEF measured from the conduction band edge is larger than that of the a-3i:H film on the surface of the a-8i:H film that forms the channel portion, located on the side opposite to the gate electrode. By providing the semiconductor film, it is possible to provide a TPT that has stable characteristics (especially in the OFF state) against the effects of external gas adsorption and processes after forming the source and drain of the TPT. Furthermore, the present invention provides a semiconductor layer (a-8
There is no unnecessary overetching of the i:H film), and the film thickness can be achieved as designed.

[Brief explanation of drawings]

Figures 1 (a) and (b) are cross-sectional views of the main parts of a conventional TPT, Figures 2 (Mb) and (C) are band structure diagrams of a conventional TPT, and Figures 3 (a) and (b) are FIGS. 4 and 6 are cross-sectional views of the main parts of the TPT according to the embodiment of the present invention, and FIGS. 6 and 6 are band structure diagrams of the TPT according to the present invention, respectively.
Figures 8(a), (b), and 9(a) to (e) are cross-sectional views of the main parts of the TPT of the present invention, and Figure 7 is a cross-sectional view of the TPT of the present invention.
FIG. 2 is a diagram showing drain current-gate voltage characteristics of FIG. 1...Substrate, 2...Gate electrode, 3...
・・Gate insulating film, 4.16・---a-3i:H film,
5,5a. 6 b ----n” doped a-3t:H film, 6+6a
, eb...source, drain electrode, 11...
... an a-8i:H film or an a-8i compound semiconductor film containing at least one element among boron, carbon, nitrogen, and oxygen. Name of agent: Patent attorney Toshio Nakao
1 Figure (α) (1) (b Figure 2 (a-) Figure 2 (C) Figure 3 (α9 (11) (b) 2 / 5th Figure 6 (0L) Figure 6 (e) ) l ? Figure 9 (6)

Claims (6)

[Claims] (1) Conduction band energy The Fermi level energy (EC-Ef) measured from EC is the first
1. A thin-film field-effect semiconductor device comprising a second semiconductor thin film having a higher Fermi level energy than that of the semiconductor thin film. (2) The thin film field effect semiconductor device according to claim 1, characterized in that the second semiconductor thin film is doped with a group Ⅰ element such as holon as an impurity. (3) The energy gap Eg of the second semiconductor thin film is
2. The thin film field effect semiconductor device according to claim 1, wherein the energy gap is larger than the energy gap of the first semiconductor thin film. (4) When manufacturing a non-single-crystal semiconductor thin-film field effect transistor mainly composed of silicon with an inverted staggered structure, after the process of selectively depositing source and drain electrodes, one of boron, carbon, nitrogen, and oxygen is removed. The method includes the steps of: depositing a second non-single crystal semiconductor film mainly composed of silicon containing at least one element; and leaving the second semiconductor film between at least the source and train electrodes. A method for manufacturing a thin film field effect semiconductor device. (5) When manufacturing a non-single-crystal semiconductor thin-film field-effect transistor with an inverted staggered structure and whose main component is silicon, after the step of selectively depositing the source and train electrodes, the source and drain electrodes are used as masks. Boron is added to the non-single crystal semiconductor thin film. A method for manufacturing a thin film field-effect semiconductor device, which includes a step of implanting at least one element among carbon, nitrogen, and oxygen using an ion implantation method. (6) A gate insulating film, a first non-single crystal semiconductor film mainly composed of silicon, and at least one of boron, carbon, oxygen, and nitrogen on the substrate on which the gate electrode is selectively deposited. A second non-single-crystalline semiconductor film mainly composed of silicon containing the above elements, a third intrinsic-type non-single-crystalline semiconductor film, and a fourth n-type non-single-crystalline semiconductor film are successively formed. 1. Second. a step of patterning third and fourth non-single crystal semiconductor films; after selectively depositing and forming source and drain electrodes, using the source and drain electrodes as a mask, the third layer extends between the source and the train; ．． A method for manufacturing a thin film field effect semiconductor device, including a step of removing a fourth non-single crystal semiconductor film.