JPH01309378A - Thin-film semiconductor element - Google Patents

Abstract

PURPOSE:To prevent a leakage current from being increased and to obtain a thin-film semiconductor element whose stability is excellent by a method wherein a concentration of an impurity element to be doped to an ohmic contact layer is made larger on the opposite side of a semiconductor layer than on the side of the semiconductor layer. CONSTITUTION:A thin-film semiconductor element is formed in the following manner: a semiconductor layer 4 whose parent body is a silicon atom and an ohmic contact layer 5 which is laminated and formed on this semiconductor layer 4 and which has been doped with an impurity element are included; the impurity element is doped in such a way that a concentration on the opposite side of the semiconductor layer becomes high as compared with the concentration on the side of the semiconductor layer 4. In this thin-film semiconductor element, the concentration of the impurity element in the ohmic contact layer 5 is higher on the surface side than on the side of the semiconductor layer 4; accordingly, a diffusion amount of phosphorus from the ohmic contact layer 5 to the semiconductor layer 4 is small. As a result, a leakage current in the ohmic contact layer 5 is not increased.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a thin film semiconductor device composed of an amorphous insulating film layer, a semiconductor layer made of amorphous silicon, an ohmic contact layer, etc. .

[Conventional technology]

In recent years, amorphous silicon (hereinafter referred to as a-3
Thin Film Transistor (Thin Film Transistor) formed by laminating semiconductor layers, insulating films, etc.
Thin film semiconductor devices such as TOR) have been put into practical use. This type of thin film semiconductor element is suitable as a driving element for an active matrix type liquid crystal display.

In an active matrix liquid crystal display, each pixel is driven independently to control the display, so each pixel can be driven with a relatively large amount of power, and the contrast ratio of the pixels is increased, so a beautiful screen display is possible. In particular, thin film transistors using A-3T (hereinafter referred to as A-3I), which have the advantage of being able to be manufactured at low cost, are used as driving elements for active matrix liquid crystal displays.
TFT) is used.

FIG. 5 is a cross-sectional structural diagram of one element of a conventional a-5i TFT, in which 1 indicates a glass substrate and 2 indicates a gate electrode patterned on the glass substrate 1. In FIG. On the upper surface of the glass substrate 1 including the surface of the gate electrode 2, a gate insulating film 3. a-
A 5i semiconductor layer 4 and an n''a-3i atomic contact layer 15 are laminated in this order.The n''a-3i atomic contact layer 15 has a portion above the gate electrode 2 removed. Further, a source electrode 6 and a drain electrode 7 are formed on the upper surface of the n''a-Si ohmic contact N15 with a gap of an appropriate width in between.

The manufacturing process of the a-5t TFT having such a configuration is as follows. After patterning the gate electrode 2 on the glass substrate 1, it is mounted on a plasma CVD apparatus and the substrate temperature is raised to around 300°C, and a gate insulating film 3. a-Si semiuniform N4 and n.

An a-Si ohmic contact layer 15 is continuously formed.

Thereafter, the substrate is taken out from the plasma CVD apparatus, and the n''a-Si ohmic contact layer 15 is etched by photolithography to form a channel section.Finally, a metal such as Cr/A1 is etched into the n''a-5t ohmic contact layer. Layer 15 is deposited to form source electrode 6 and drain electrode 7.

By the way, the n''a-Si ohmic contact layer has the function of facilitating the transport of electrons induced in the channel to the source or drain electrode, and the function of blocking the flow of holes induced in the channel (off-state current). It is usually formed from a phosphine gas (PI+3) containing an element belonging to Group V of the periodic table, especially P, and a monosilane gas (SiH4).

[Problem to be solved by the invention]

a-5i Although TFT is an n-channel FET (field effect transistor) in which carrier movement is mainly caused by electrons, when the gate voltage is made negative, the drain current increases, in other words, the off-state current increases and S A phenomenon in which the /N ratio decreases occurs, and the following three points can be considered as the causes of such a phenomenon. First of all
The point is that since n''a-Si is used as the ohmic contact layer, the positive voltage induced by a negative gate voltage will flow over the barrier of the junction and flow toward the source or drain electrode. So, the second point is a-5
Since there are many trap levels at the interface between i and n''a-Si or within n''a-5i, carriers are released from these trap levels and become a leak current.
The third point is that leakage current can easily flow due to the resistance of a portion of the channel being lowered.

As described above, when the leakage current of the ohmic contact layer increases, the display characteristics of a liquid crystal display (LCD) deteriorate. In other words, in an a-Si TFT LCD, characters or images are displayed by holding charge in the liquid crystal (LC) layer for a certain period of time, but if the leakage current is large, the charge may accumulate in the liquid crystal layer. It becomes impossible to maintain the generated charge for a certain period of time, resulting in a decrease in contrast ratio.

Therefore, in order to obtain a high contrast ratio in a liquid crystal display, it is necessary to manufacture a-5i TPT, which has characteristics such as stable and low leakage current (off current), as the a-Si TFT that drives it. be.

The present invention was made in view of such circumstances, and it is possible to reduce the concentration of impurity elements added to the ohmic contact layer.
It is an object of the present invention to provide a thin film semiconductor element with excellent stability by preventing an increase in leakage current by making the size larger on the opposite side of the semiconductor layer than on the side of the semiconductor layer.

[Means to solve the problem]

Here, the cause of the increase in leakage current will be explained in relation to the manufacturing process of the a-3T TFT. As mentioned above, in the n''a-Si ohmic contact layer formed on the a-Si semiconductor layer using a mixed gas of phosphine gas and silane gas, the portion corresponding to the channel portion is etched.
A portion where a source electrode or a drain electrode will be formed remains. In order to obtain good characteristics, the substrate temperature during formation is 200 to 300°C. Since phosphorus (P) contained inside n''a-5i easily diffuses inside a-5i, phosphorus also diffuses inside a-5i. Therefore, by etching, one atomic contact of n''a-3i is made. Phosphorus also diffuses to the a-3i surface of the channel portion from which the layer has been removed, and the dark resistivity of a-3i of the channel portion decreases, resulting in an increase in leakage current.

One possible method for preventing the above-mentioned diffusion of phosphorus is to lower the substrate temperature during film formation.
In this case, since phosphorus is not electrically activated in the film at low temperatures, there is a drawback that the dark specific resistance of the n''a-5i portion does not decrease.

Therefore, when forming the ohmic contact layer, the substrate temperature is
a-5 maintained at 00 to 300°C and configured to prevent phosphorus in n''a-3i from diffusing into a-5t.
It is necessary to manufacture i TFTs.

Therefore, in the a-3i TFT of the present invention, the ohmic contact layer is made of a laminate in which a layer with a low phosphorus concentration and a layer with a high phosphorus concentration are laminated in this order from the a-3i semiconductor layer side. or a-S
The ohmic contact layer is such that the phosphorus concentration increases continuously as it moves away from the interface with the i-semiconductor layer.

In other words, the a-3t TFT of the present invention has an ohmic contact layer in which the phosphorus concentration is low on the side in contact with the a-5i semiconductor layer, and the phosphorus concentration is high on the opposite side. Then, since the phosphorus concentration on the side in contact with the a-Si semiconductor layer is low, the amount of phosphorus diffused into the a-5i semiconductor layer is reduced compared to the conventional case. In addition, when etching and notching the ohmic contact I layer, conventionally the amount of phosphorus diffused was large, so it was necessary to strictly control etching from the interface of the a-5i semiconductor layer, but in the present invention, the amount of phosphorus diffused Since the amount of etching is small, the tolerance for the amount of etching near the interface is increased, and the manufacturing process is facilitated.

The thin film semiconductor device according to the present invention includes a semiconductor layer having silicon atoms as a host, and an ohmic contact layer laminated on the semiconductor layer and doped with an impurity element. The impurity element is added so that the concentration on the side opposite to the semiconductor layer is higher than the concentration on the side of the layer.

[Effect]

In the thin film semiconductor device according to the present invention, the concentration of the impurity element in the ohmic contact layer is higher on the surface side than on the semiconductor layer side. Therefore, the amount of phosphorus diffused from the ohmic contact layer to the semiconductor layer is small. As a result, leakage current in the ohmic contact layer does not increase.

〔Example〕

Hereinafter, the present invention will be explained based on drawings showing embodiments thereof.

FIG. 1 is a cross-sectional structural diagram of a thin film semiconductor device according to the present invention, and numeral 1 in the figure indicates a glass substrate. A gate electrode 2 made of Cr is patterned on the upper surface of the glass substrate 1 . The layer thickness of the gate electrode 2 is set to 300 to 3000 layers, more preferably 500 to 1500 layers. Note that the gate electrode 2 may be formed of Mo+Ta, AI, Ni-Cr, or a laminate of these. A gate insulating film 3 made of SiNx is formed on the upper surface of the glass substrate 1 including the surface of the gate electrode 2.
is formed. The thickness of the gate insulating film 3 is 500 to 5
000 people, more preferably 1000 to 3000 people. The colored film 3 on the gate is made of SiOx.

It may be formed from SiOxNy, TazOs, AlzOr, or a laminate thereof. Further, an a-5i semiconductor layer 4 is laminated on the upper surface of the gate insulating film 3. a-
The thickness of the 5i semiconductor layer 4 greatly affects the off-state current of the TFT and the amount of current during light irradiation, but is usually 200 to 400 mm.
0 people, more preferably 500 to 3000 people.

An ohmic contact layer 5 is laminated on the upper surface of the a-5i semicircular body layer 4 except for the portion where the gate electrode 2 is formed. The ohmic contact layer 5 consists of a two-layer stack, the lower layer is a layer 5a with a low phosphorus concentration (hereinafter referred to as the low phosphorus layer 5a), and the upper layer is a layer 5b with a high phosphorus concentration (
(hereinafter referred to as high phosphorus JW5b). In order to minimize the diffusion of phosphorus into the a-3i semiconductor layer 4 even at a substrate temperature of about 300°C, the phosphorus concentration of the low phosphorus layer 5a is 0 to 10-2 atomic %, more preferably 10 -6～
Since the flat phosphorus layer 5b needs to have the same function as a conventional low-resistance ohmic contact layer, its phosphorus concentration is preferably 10'':1 to 5 at%. The electrical characteristics of the low phosphorus layer 5a are such that the dark specific resistance (ρ6) is 10"
~105Ω・cm, more preferably 1010~1
06 Ω・cm, and the activation energy (E, ) is 0.
．． 1 to 0.4 eV, more preferably 0.7 to 0.5
Let it be eV. On the other hand, the electrical characteristics of the high phosphorus layer 5b are such that the dark specific resistance is 10 h to 10 Ω·cm, more preferably 10 h to 10 Ω·cm.
5~102 Ω・CI! 1 eV, and the activation energy is 0.5 to 0.1 eV, more preferably 0.4 to 0.1 eV.
It is set to 2eV. The thickness of the contact layer 5 is usually 100 to 2000, more preferably 300 to 2000.
Let's say 1000 people. Also, the low phosphorus layer 5a and the high phosphorus layer 5b
The layer thickness ratio of the low phosphorus layer 5a is 50% or less of the total layer thickness of the ohmic contact layer 5, and more preferably 30% or less.

On the upper surface of the ohmic contact layer 5 (high phosphorous layer 5b), a Cr layer 20. A source electrode 6 and a drain electrode 7 each having a stacked structure of an AI layer 21 are formed. The source electrode 6 and the drain electrode 7 usually have a laminated structure of high melting point metal and AI, and in addition to the above-mentioned Cr/AI, Mo/AL Ti
/AI, etc. combinations are used. The film thickness of high melting point metal is 1
00 to 1000 people, more preferably 100 to 500 people, and the film thickness of A1 is 2000 people to 2 μm, more preferably 5000 people to 1.5 μm.

Next, a method for manufacturing an a-3t TFT having such a structure will be explained based on FIG. 2 showing the process.

On a thoroughly cleaned 5 inch square glass substrate 1, Cr is deposited to a thickness of 1000 ml, and a gate electrode 2 is patterned by photoetching (FIG. 2(a)).

Note that the channel length of TPT is 10 μm and the width of one channel is 200 μm.

The glass substrate 1 on which the gate electrode 2 is formed is exposed to plasma C.
The glass substrate 1 is installed in a VD apparatus, and while the inside of the CVD apparatus is evacuated by a diffusion pump, the glass substrate 1 is heated and adjusted to 300°C. The degree of vacuum inside the CVD equipment is 1 x 10-6 Torr
When the temperature is below, switch from the diffusion pump to the mechanical booster pump and introduce 100% monosilane gas into the CVD equipment via the mass flow controller for 8 seconds.
ecm, ammonia gas (Nlh) at 40 sec,
Nitrogen gas (N2) was introduced for 80 seconds, and the reaction pressure was 0.
．． Adjust to 5 Torr. With the gas flow rate and internal pressure stabilized in this manner, the RF power of 13.56 MIIz is maintained at 50 W and applied alternately for 20 minutes to form the gate insulating film 3. The gate insulating film 3 thus obtained has a refractive index of 1.82, an optical band gap (E9) of 5.1 eV, a dielectric constant of 6.1, and a film thickness of 3000 nm.

Next, an a-Si semiconductor layer 4 is laminated to a thickness of 2000 mm on the gate insulating film 3 in the same plasma CVD apparatus. The formation conditions at this time were that the flow rate of 100% monosilane gas was los ccm, the reaction pressure was 0.2 Torr, and R
The F power was 100 W and the application time was 13 minutes.

The electrical properties of the a-3i semiconductor layer 4 obtained in this way include a dark specific resistance of 2 x 10" Ωcm, an activation energy of 0.7 eν, and an optical property that an optical band gap of 1
, 75 eV.

Next, a low phosphorus layer 5a and a high phosphorus layer 5b constituting the ohmic contact layer 5 are laminated in this order on the a-3i semiconductor layer 4 (FIG. 2(b)). The formation conditions for the low phosphorus layer 5a are that the flow rate of 100% monosilane gas is 101
05e, 10ppm hydrogen gas (N2) Hose's phosphine gas flow rate is 10105e, reaction pressure is 0.2To
rr, the RF power is 100 W and the application time is 2 minutes. On the other hand, the formation conditions for the crystal phosphorus layer 5b are 100
The flow rate of % monosilane gas is 10105c, the flow rate of phosphine gas with 1% hydrogen gas space is 10105e, the reaction pressure is 0.2 Torr, the RF power is 100 W, and the application time is 3 minutes. The thickness of the low phosphorus layer 5a obtained in this way is 200 layers, the electrical characteristics are as follows: dark specific resistance is 107 Ω·cm, activation energy is 0.55 cV, and - The layer thickness of layer 5b is 300, and the electrical characteristics are as follows: dark specific resistance is 3×10zΩ・
mark, activation energy is 0.2 eV.

Next, after lowering the substrate temperature to about 70°C, the glass substrate 1 that has undergone the above treatment is taken out from the plasma CVD apparatus and placed in a vacuum evaporation apparatus, and Cr is deposited to a thickness of 30°C.
Vapor deposition is performed by 0 people (Fig. 2 (C)). Next, using photolithography, the Cr layer 20 above the channel is etched with acid, and the ohmic contact layer 5 is etched with a hydrofluoric acid etching solution (FIG. 2(d)). After cleaning and drying, it is again placed in the vacuum deposition apparatus and A1 is deposited to a thickness of 1.0 μm. Thereafter, using a photolithography method, the AI layer 21 above the channel is etched with a phosphoric acid aqueous solution, and the Cr layer 20. AI layer 21
Form a source electrode 6 and a drain electrode 7 consisting of (
Figure 2(e)).

As a result of measuring the characteristics of the a-Si TFT manufactured as described above, the field effect mobility was 0.6cnl/
Vsec, the threshold voltage is 1.5■, and the drain voltage is IOV, the drain current when the gate voltage is 15V is 2X10-'A, and the gate voltage is O
The drain current when set to V was 5 x lQ-13A. Also, when the gate voltage is -10■, the off-state current when the drain voltage is 10V is 7X10-''A,
Off-state current when drain voltage is 20V is 9 x 1
It was Q-13A.

By the way, the conventional a-3i TFT was manufactured under the same conditions as the above-mentioned example except that all the ohmic contact layers were composed of high phosphorous layers, that is, n''a-5i.
(The layer thickness of the n″a-5i atomic contact layer is 5
00)'s ♀h characteristics are as follows. Field effect mobility is Q, 7cnl/Vsec, threshold voltage is 1.
2V and the drain voltage is 10■, the drain current when the gate voltage is 15V is 3XIO
The drain current was 5 Xl0-''A when the gate voltage was 0. Also, the gate voltage is -10
V, the off current when the drain voltage was IOV was 2×10 −12 A, and the off current when the drain voltage was 20 V was 8×1 O−I2 A.

As understood from the above results, the a-3iTF of the present invention
The TFT has improved off-current characteristics compared to the conventional a-5i TFT.

Note that in the above embodiment, the ohmic contact layer is composed of a two-layer stack of a low phosphorus layer and a high phosphorus layer, but the present invention is not limited to this, and the phosphorus concentration on the a-St semiconductor layer side is lower. In this case, various other embodiments can be considered. FIG. 3.4 is a graph showing the distribution of phosphorus concentration in another example, where the vertical axis shows the distance from the interface with the a-5i hemilateral layer, and the horizontal axis shows the phosphorus concentration.

In the example shown in FIG. 3, phosphorus in the ohmic contact layer increases as the distance from the interface with the a-3i semiconductor layer increases. This shows a case where the seismic intensity increases continuously. In the example shown in Figure 4, the phosphorus concentration in the ohmic contact layer increases in a stepwise manner. The example shown shows a case where six layers are laminated.

〔Effect of the invention〕

As detailed above, in the thin film semiconductor device of the present invention, it is possible to improve off-current characteristics without substantially deteriorating transistor characteristics.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional structural diagram of a thin film semiconductor device according to the present invention, Fig. 2 is a schematic diagram showing its manufacturing process, Fig. 3-4 is a graph showing the distribution of phosphorus concentration in another example, and Fig. 5 is a cross-sectional structural diagram of a conventional thin film semiconductor element. 1...Glass base + anti-2...Gate electrode 3...
Gate bag edge film 4... a-3i semiconductor layer 5... Ohmic contact B 5a... low phosphorus layer 5b.
...High phosphorous layer 6...Source electrode 7...Drain electrode Patent Applicant: Sumitomo Metal Industries Co., Ltd. Representative Patent Attorney: Noboru Kawano Figure 2

Claims (1)

[Scope of Claims] 1. In a thin film semiconductor element having a semiconductor layer containing silicon atoms as a matrix and an ohmic contact layer laminated on the semiconductor layer and doped with an impurity element, on the semiconductor layer side: A thin film semiconductor device, characterized in that the impurity element is added such that the concentration on the side opposite to the semiconductor layer is higher than the concentration on the side opposite to the semiconductor layer.