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JPS60116160A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60116160A
JPS60116160A JP22503983A JP22503983A JPS60116160A JP S60116160 A JPS60116160 A JP S60116160A JP 22503983 A JP22503983 A JP 22503983A JP 22503983 A JP22503983 A JP 22503983A JP S60116160 A JPS60116160 A JP S60116160A
Authority
JP
Japan
Prior art keywords
temperature
layer
film
vapor phase
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22503983A
Other languages
Japanese (ja)
Inventor
Takao Kobayashi
孝夫 小林
Koji Nagai
永井 幸二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP22503983A priority Critical patent/JPS60116160A/en
Publication of JPS60116160A publication Critical patent/JPS60116160A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the temperature dependency by forming a sllicon layer by reduced-pressure vapor phase growing method of the prescribed temperature or lower on an insulating film of the substrate and forming a silicon layer implanted with impurity as a resistor, thereby increasing the gray size. CONSTITUTION:An insulating film 2 is formed by silicon oxidation on a semiconductor substrate 1, and a polycrystalline silicon layer 3 is formed by reduced- pressure vapor phase growing method at 580 deg.C or lower on the film 2. Then, an impurity is doped in the layer 3 by the prescribed treatment to form a resist film, then the resist film is selectively removed by a photoetching. Then, with the remaining resist film as a mask the layer 3 is etched by plasma in the desired shape. Then, an insulating film 4 is formed on the layer 3, it is then heat treated at the prescribed temperature range to activate the impurity, thereby increasing the gray size to reduce the temperature dependency of the resistor.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は新規な半導体装置の製造方法に関し、特に多結
晶シリコンにより温度依存性の小さな抵抗体を形成する
ことのできる新規な半導体装置の製造方法を提供しよう
とするものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a novel method for manufacturing a semiconductor device, and in particular to a method for manufacturing a novel semiconductor device that can form a resistor with small temperature dependence using polycrystalline silicon. This is what we are trying to provide.

背景技術とその問題点 モノリシックICに多結晶シリコンからなる抵抗を形成
する技術があるが、その抵抗の形成は一般的に次のよう
に行われていた。
BACKGROUND ART AND PROBLEMS There is a technique for forming a resistor made of polycrystalline silicon in a monolithic IC, but the resistor is generally formed as follows.

半導体基板表面の絶縁膜上に減圧気相成長法により60
0〜660’Oの温度下で多結晶シリコン層を形成し、
次いで、該多結晶シリコン層に導電性不純物をドーピン
グし、次に活性化熱処理し、その後多結晶シリコン層を
選択的にエツチングして所定のパターンにするという順
序で抵抗が形成てれる。
60% by low pressure vapor phase growth method on the insulating film on the surface of the semiconductor substrate.
forming a polycrystalline silicon layer at a temperature of 0 to 660'O;
A resistor is then formed by doping the polycrystalline silicon layer with conductive impurities, followed by activation heat treatment, and then selectively etching the polycrystalline silicon layer into a predetermined pattern.

ところで、このように形成した多結晶シリコンからなる
抵抗は負の抵抗温度係数を持ち、その抵抗温度係数の絶
対値は比抵抗が大きくなる程大きくなるという問題があ
った。
However, there is a problem in that the resistor made of polycrystalline silicon formed in this manner has a negative temperature coefficient of resistance, and the absolute value of the temperature coefficient of resistance increases as the specific resistance increases.

発明の目的 しかして、本発明は多結晶シリコンにより温度依存性の
小さな抵抗体を形成することのできる新規な半導体装置
の製造方法を提供しようとするものである。
OBJECTS OF THE INVENTION It is therefore an object of the present invention to provide a novel method for manufacturing a semiconductor device in which a resistor with small temperature dependence can be formed using polycrystalline silicon.

発明の概要 上記目的を達成するため本発明半導体装置の製造方法は
、半導体基板の表面に形成された絶縁膜上に580℃以
下の温度下で減圧気相成長法によりシリコン層を形成し
、該シリコンjだ・に不純物を導入して該シリコン層を
抵抗体とすることを特徴とするものである。
Summary of the Invention In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes forming a silicon layer on an insulating film formed on the surface of a semiconductor substrate by a low pressure vapor phase epitaxy method at a temperature of 580° C. or lower; The feature is that impurities are introduced into the silicon layer to make the silicon layer a resistor.

実施例 以下に、本発明半導体装置の製造方法を添ト14図面に
示した実施例に従って詳細に説明する第1図(A)〜(
D)は本発明半導体装置の製造方法の一例を製造工程順
に示す半導体基板の断面図である。
EXAMPLE The method for manufacturing a semiconductor device of the present invention will be explained in detail in accordance with the example shown in the attached 14 drawings.
D) is a cross-sectional view of a semiconductor substrate showing an example of a method for manufacturing a semiconductor device of the present invention in the order of manufacturing steps.

(A)単結晶のシリコンから成るウェノ\状の半導体基
板1の上面に熱酸化あるいは気相成長法によ体てシリコ
ン酸化膜2を形成する。このシリコン酸化膜2の形成工
程は多結晶シリコンからなる抵抗を形成するためだけの
!特別の工程ではなく、バイポーラI・ランジスタ等の
形成工程の一部を成す。
(A) A silicon oxide film 2 is formed on the upper surface of a wafer-shaped semiconductor substrate 1 made of single crystal silicon by thermal oxidation or vapor phase growth. This step of forming silicon oxide film 2 is only for forming a resistor made of polycrystalline silicon! It is not a special process, but forms part of the process for forming bipolar I transistors, etc.

(B)次に、上記シリコン酸化膜2の上面に減圧気相成
長法によって例えばシラン化合物等のガスの熱分解によ
り、多結晶シリコン層3を形成する。この気相成長は従
来のような600〜680°Cの温度で行)のではなく
、580″C以下例えば540°Cで行う。
(B) Next, a polycrystalline silicon layer 3 is formed on the upper surface of the silicon oxide film 2 by thermal decomposition of a gas such as a silane compound by low pressure vapor phase growth. This vapor phase growth is not performed at a temperature of 600 to 680°C as in the conventional method, but is performed at a temperature of 580″C or lower, for example, 540°C.

(C)次に、例えばイオンインプランテーシ運ン、ドー
プドオキサイド、プレデポジション等により多結晶シリ
コン層3に不純物をドープする処理を行う。
(C) Next, the polycrystalline silicon layer 3 is doped with an impurity by, for example, ion implantation, doped oxide, pre-deposition, or the like.

(D’)次に、レジスト膜を形成し、写真処理によりレ
ジスト膜を選択的に除去し、残存するレジスト膜をマス
クして多結晶シリコン層3をCF4プラズマ等によりエ
ツチングして所望の形にする。
(D') Next, a resist film is formed, the resist film is selectively removed by photo processing, the remaining resist film is masked, and the polycrystalline silicon layer 3 is etched using CF4 plasma or the like to obtain the desired shape. do.

次いで、不純物のアウトディヒユージョンの防止、表面
保護、酸化防止等の目的のため多結晶シリコン層3表面
にシリコン酸化膜等の絶縁性被膜4を形成し、その後6
00〜1100’Oの範囲内の適宜の温度で熱処理して
不純物を活性化する。
Next, an insulating film 4 such as a silicon oxide film is formed on the surface of the polycrystalline silicon layer 3 for the purpose of preventing out-diffusion of impurities, protecting the surface, and preventing oxidation.
The impurities are activated by heat treatment at an appropriate temperature within the range of 00 to 1100'O.

しかる後、該被膜4を選択的にエツチングすることによ
り電極取り出し用の窓5を形成し、その、後、電極6を
半導体基板1上に形成する。
Thereafter, the film 4 is selectively etched to form a window 5 for taking out the electrode, and then an electrode 6 is formed on the semiconductor substrate 1.

このように、気相成長法により多結晶シリコン膜3を形
成するときの温度を580℃以下例えば540°Cにす
ることによって抵抗体の温度依存性を小さくすることが
できる。第2図は多結晶シリコン膜3を気相成長すると
きの温度を540°Cにした場合と従来のように650
°Cにした場合の抵抗の温度特性を示すものである。こ
の特性は多結晶シリコン膜3の膜厚が1000人、ドー
プした不純物がリンP、抵抗率pがIonΩ・Cmとい
う条件下で、気相成長の時の温度のみを540°C16
50°Cと2通りに変化して抵抗体を形成したものにつ
いて測定して得たものである。
In this way, by setting the temperature at which the polycrystalline silicon film 3 is formed by vapor phase growth to 580° C. or lower, for example 540° C., the temperature dependence of the resistor can be reduced. Figure 2 shows the case where the polycrystalline silicon film 3 is grown in vapor phase at a temperature of 540°C and the conventional case where the temperature is 650°C.
It shows the temperature characteristics of resistance when it is set to °C. This characteristic is based on the conditions that the thickness of the polycrystalline silicon film 3 is 1000 nm, the doped impurity is phosphorus P, and the resistivity p is IonΩ・Cm, and only the temperature during vapor phase growth is 540°C16.
The results were obtained by measuring resistors formed at 50° C. in two ways.

この図から明らかなように、抵抗率が低い領域では多結
晶シリコン膜3の抵抗温度係数は止であるが、抵抗率が
ある程度以上高くなると抵抗温度係数は負になり、その
絶対値は抵抗率が高くなる程大きくなる。従って、多結
晶シリコン膜を抵抗体として用いるために抵抗率を高く
した場合には抵抗温度係数は負で、その絶対値は無視で
きない程大きくなるが、多結晶シリコン膜3を気相成長
させるときの温度を本発明のように通常より低い例えば
540℃にした場合には通常の例えば650°Cにした
場合よりも負の抵抗温度係数のない程度の大きさとなり
、通常の場合温度変化範囲が00C〜80°Cでは抵抗
温度係数が−1000〜−2000p p m / ”
Cとなる。しかしながら、気相成長する・ときの温度を
540 ’Cにするというように低くした場合には−5
00〜−200i)ppm10Cにすることができ、温
度依存度を2分の工程度軽減することができる。
As is clear from this figure, the temperature coefficient of resistance of the polycrystalline silicon film 3 stops in the region of low resistivity, but when the resistivity increases beyond a certain level, the temperature coefficient of resistance becomes negative, and its absolute value is the resistivity. The higher the value, the larger the value. Therefore, when the resistivity is increased to use a polycrystalline silicon film as a resistor, the temperature coefficient of resistance is negative and its absolute value becomes so large that it cannot be ignored. However, when the polycrystalline silicon film 3 is grown in a vapor phase, If the temperature is lower than normal, for example, 540°C, as in the present invention, the temperature coefficient of resistance will be smaller than the normal temperature, for example, 650°C, and the temperature change range will normally be smaller. At 00C to 80°C, the temperature coefficient of resistance is -1000 to -2000ppm/”
It becomes C. However, if the temperature during vapor phase growth is lowered to 540'C, -5
00 to -200i) ppm 10C, and the temperature dependence can be reduced by 2 minutes.

このように、シリコン膜を気相成長により形成するとき
の温度を低くするとシリコン特性が上述したように変化
するのは次の理由による。即ち、気相成長温度は一般に
気相成長速度その他の点から600〜660℃位で行わ
れているが、そのような温度では、特に620℃以上で
はそのシリコン膜は多結晶シリコン(ポリシリコン)に
なる。
The reason why silicon properties change as described above when the temperature at which a silicon film is formed by vapor phase growth is lowered is as follows. In other words, the vapor phase growth temperature is generally 600 to 660 degrees Celsius due to the vapor growth rate and other aspects. become.

そして、その後の熱処理でグレインが成長する。Then, grains grow through subsequent heat treatment.

それに対して、580°C以下の温度でシリコン膜の気
相成長処理をした場合にはその気相成長処理段階ではシ
リコン膜がアモルファスに近い状態でなる。そして、そ
の後の熱処理においてそのシリコン膜が多結晶になる。
On the other hand, when a silicon film is vapor-phase grown at a temperature of 580° C. or lower, the silicon film becomes nearly amorphous at the vapor-phase growth stage. Then, during subsequent heat treatment, the silicon film becomes polycrystalline.

そして、このようにアモルファス状態から多結晶状態へ
移行するような再結晶の進行が為された場合の方が多結
晶から多結晶へという再結晶の進行が為された場合より
もグレインサイズが大きくなり、従ってグレインバウン
ダリに沿って存在するトラップ密度も低くなる。そして
、多結晶シリコンの温度特性はトラップの温度特性に大
きく支配されて(1)るので、このトラップ密度が低い
程抵抗の温度依存度も小さくなる。
In this way, when recrystallization progresses from an amorphous state to a polycrystalline state, the grain size becomes larger than when recrystallization progresses from polycrystalline to polycrystalline. Therefore, the density of traps existing along the grain boundary is also low. Since the temperature characteristics of polycrystalline silicon are largely controlled by the temperature characteristics of the traps (1), the lower the trap density, the smaller the temperature dependence of the resistance.

発明の効果 以上に述べたように、本発明半導体装置の製造方法は、
半導体基板の表面に形成された絶縁膜上に580°C以
下の温度下で減圧気相成長法によりシリコン層を形成し
、該シリコン層に不純物を導入して該シリコン層を抵抗
体とすることを特徴とするものである。従って、本発明
によれば、シリコン膜は気相成長された段階ではアモル
ファス状態であり、その後の加熱処理されたときはじめ
て多結晶状態になる。その結果、グレインサイズが大き
くなり、グレインバウンダリに沿って存在するトラップ
の密度が低くなるので、温度依存性が小さくなる。依っ
て、温度依存性の小さな多結晶シリコンによる抵抗体を
形成することが可能である。
Effects of the Invention As stated above, the method for manufacturing a semiconductor device of the present invention has the following effects:
Forming a silicon layer on an insulating film formed on the surface of a semiconductor substrate by low pressure vapor phase growth at a temperature of 580°C or less, and introducing impurities into the silicon layer to make the silicon layer a resistor. It is characterized by: Therefore, according to the present invention, the silicon film is in an amorphous state when it is grown in a vapor phase, and becomes a polycrystalline state only when it is subjected to a subsequent heat treatment. As a result, the grain size increases and the density of traps along the grain boundaries decreases, resulting in less temperature dependence. Therefore, it is possible to form a resistor made of polycrystalline silicon with low temperature dependence.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)〜(D)は本発明半導体装置の製造方法の
実施の一例を工程順に示す半導体基板の断面図、第2図
は抵抗温度係数と抵抗率との相関関係を第1図に示した
方法により形成した多結晶シリコンからなる抵抗と従来
の方法により形成した多結晶シリコンからなる抵抗とに
ついて示す図である。 符号の説明 i−・ゆ半導体基板、2・・・絶縁膜、・争・(多結晶
)シリコン膜
1A to 1D are cross-sectional views of a semiconductor substrate showing an example of the method for manufacturing a semiconductor device of the present invention in the order of steps, and FIG. 2 is a diagram showing the correlation between the temperature coefficient of resistance and resistivity. FIG. 3 is a diagram showing a resistor made of polycrystalline silicon formed by the method shown in 1 and a resistor made of polycrystalline silicon formed by a conventional method. Explanation of symbols: i--semiconductor substrate, 2--insulating film, (polycrystalline) silicon film

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板の表面に形成された絶縁膜上に580
℃以下の温度下で減圧気相成長法によりシリコン層を形
成し、該シリコン層に不純物を導入して該シリコン層を
抵抗体とすることを特徴とする半導体装置の製造方法
(1) 580 nm on the insulating film formed on the surface of the semiconductor substrate.
A method for manufacturing a semiconductor device, comprising forming a silicon layer by low pressure vapor phase growth at a temperature of 0.degree. C. or lower, and introducing impurities into the silicon layer to make the silicon layer a resistor.
JP22503983A 1983-11-29 1983-11-29 Manufacture of semiconductor device Pending JPS60116160A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22503983A JPS60116160A (en) 1983-11-29 1983-11-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22503983A JPS60116160A (en) 1983-11-29 1983-11-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60116160A true JPS60116160A (en) 1985-06-22

Family

ID=16823088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22503983A Pending JPS60116160A (en) 1983-11-29 1983-11-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60116160A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1065715A2 (en) * 1999-07-01 2001-01-03 Intersil Corporation Bicmos process with low temperature coefficient resistor (TCRL)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5030423A (en) * 1973-07-17 1975-03-26
JPS50113169A (en) * 1973-10-29 1975-09-05
JPS50134782A (en) * 1974-04-15 1975-10-25
JPS50134781A (en) * 1974-04-15 1975-10-25
JPS5516444A (en) * 1978-07-24 1980-02-05 Hitachi Ltd Producing method of semiconductor thin film resistance
JPS57106101A (en) * 1980-12-24 1982-07-01 Tokyo Shibaura Electric Co Method of producing semiconductor resistance element
JPS59182554A (en) * 1983-04-01 1984-10-17 Hitachi Ltd Semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5030423A (en) * 1973-07-17 1975-03-26
JPS50113169A (en) * 1973-10-29 1975-09-05
JPS50134782A (en) * 1974-04-15 1975-10-25
JPS50134781A (en) * 1974-04-15 1975-10-25
JPS5516444A (en) * 1978-07-24 1980-02-05 Hitachi Ltd Producing method of semiconductor thin film resistance
JPS57106101A (en) * 1980-12-24 1982-07-01 Tokyo Shibaura Electric Co Method of producing semiconductor resistance element
JPS59182554A (en) * 1983-04-01 1984-10-17 Hitachi Ltd Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1065715A2 (en) * 1999-07-01 2001-01-03 Intersil Corporation Bicmos process with low temperature coefficient resistor (TCRL)
EP1065704A2 (en) * 1999-07-01 2001-01-03 Intersil Corporation Low temperature coefficient resistor (TCRL)
EP1065715A3 (en) * 1999-07-01 2005-01-05 Intersil Corporation Bicmos process with low temperature coefficient resistor (TCRL)
EP1065704A3 (en) * 1999-07-01 2005-01-12 Intersil Corporation Low temperature coefficient resistor (TCRL)

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