JPS60103715A - Automatic equalizer - Google Patents

Abstract

PURPOSE:To obtain an excellent equalizing performance with a small order number by controlling the amount giving a base of an exponential function having an exponential function unit sample response and its weight in digital transmission to improve the matching with a subscriber line. CONSTITUTION:A signal having a distortion through a transmission line is sampled at a sufficient speed without losing required information at an A/D converting circuit 2 at first and converted into a digital signal such as PCM. The digital signal is added with a signal multiplied (5) with weights W1, W2,...,WM through circuits 111, 112,...11M having an exponential function unit sample response respectively. In this case, the equalization is attained by controlling the base a1, a2,...aM of the exponential function of the unit sample response of the circuits 111, 112,...,11M and the weights W1, W2,...,WM to minimize the interference between codes at the signal of the equalizer output terminal 7 by the control circuit 13.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an automatic equalizer that automatically equalizes lines in accordance with transmission line conditions in Dinocle transmission.

(Prior Art) When performing dinotal wired transmission, it is necessary to equalize the characteristics of the transmission line, which vary depending on the type, length, etc. of the transmission line, using an automatic equalizer having a variable function.

With the recent progress in dinotal signal processing technology and LSI technology, dinotalization of transmission circuit networks including automatic equalizers is being actively studied.

FIG. 1 is a block diagram of this type of automatic equalizer that has been conventionally tested. In Figure 1, 1 is an analog signal input terminal, 2 is an analog/digital conversion circuit, 3 is an equal right-aligned input terminal, 4 is a delay circuit, 5 is a multiplication circuit, 6 is an addition circuit, and 7 is an equal right-aligned input terminal. 8 is a data identification judgment circuit, 9 is an identification data output terminal, 10 is a weight control circuit, WOr W+ + W2 + . . . , wM is a weight. When the distorted signal that has passed through the transmission line is input to the analog signal input terminal 1, it is first sampled by the analog-to-digital conversion circuit 2 at a sufficient speed without losing necessary information. For example, it is converted into a digital signal such as PCM. This digital signal is 0
are passed through M delay circuits 4, each with a weight W. .

WI + w21..., multiplied by wM and then added. At this time, the weight control circuit 1o gives equal output terminal 7.
The weight Wo is set so that the code amount interference in the signal of
,W, ,W2. ...l Equalization is performed solely to control the WM. All operations after the signal is converted into a digital signal by the analog-to-digital conversion circuit 2 are performed by digital calculations and processing.

However, when equalizing the characteristics of a transmission line with relatively large distortion, such as a subscriber line, using a circuit as shown in FIG.
As a result, the circuit scale is large, power consumption increases,
This has the disadvantage of increasing the chip area when integrated.

(Object of the Invention) In order to eliminate these drawbacks, the present invention has an automatic transmission function that has a transmission function that closely matches the transmission characteristics of the subscriber line and that obtains sufficient equalization with a simple configuration of low order. This realizes an equalizer.

(Structure of the Invention) The present invention comprises a plurality of circuit networks each consisting of a circuit having an exponential unit sample response and a multiplier circuit that changes the size by multiplying the output of the circuit by a weight; or an automatic equalizer configured with an adder circuit that adds each output of a plurality of circuit networks and the input of the automatic equalizer, or an adder circuit that adds only each output of the plurality of circuit networks, and an exponential unit sample. An automatic equalizer comprising a circuit having a response and a multiplication circuit that changes the size by multiplying the output of the circuit by a weight, the circuit having an exponential unit sample response of each automatic equalizer. It controls the quantity that provides the base of the exponential function and the weight.

(Embodiment) FIG. 2 shows a first embodiment of the automatic equalizer of the present invention. In FIG. 2, 111+112+..., 11M are exponential unit sample responses α minus α2k, respectively.

. . ., a circuit having αMk, 121 + 122+・
..., 12M is the output terminal of each circuit, 13 is the circuit 111
+112+...

The base α1 of the exponential function of the unit sample response of 11M. α2°..., αM and Wl, W2. ...+ WM'e
1. Other symbols have the same meanings as those in FIG. 1. k represents sampling.

The signal that has caused distortion through the transmission line is first sampled by the analog-to-digital conversion circuit 2 at a sufficient speed without losing necessary information, and is converted into a digital signal such as PCM, for example. be done. This digital signal is then summed with the signal multiplied by the circuits 111°112+-+71M k-way weights W/l lW2, -, wMi, each having an exponential unit sample response. At this time, in the control circuit 13, the circuits 111, 11□, . The base α1 of the exponential function of the unit sample response of IM. α2. ..., αM and weight W,
, W2. ..., WM (!-). Equalization is performed by controlling. All operations after being converted into a digital signal by the analog-to-digital conversion circuit 2 are performed by dinotal calculations and processing.

In Figure 3, a circuit 1 with an exponential unit sample response is shown.
11 specific configuration methods are shown below. α1 is a weight corresponding to the base of the exponential function of the exponential unit sample response, and the other symbols have the same meanings as those in FIGS. 1 and 2. Although FIG. 3 shows the circuit 11□ in the first stage as a representative, the same applies to the circuits in the other stages. Since the transmission characteristic of the circuit in Fig. 3 is, the unit sample response of this circuit is hi-α
, k (2), it is confirmed that the circuit of FIG. 3 is equivalent to circuit 1c.

In FIG. 2, circuits 111, 112, . . . , 1
Weight α1 + α2 r ”' r αM and weight W corresponding to the base of 4 JiJ numbers of 1M unit sample response
l + W2 +-1 As the WMO control algorithm, the maximum slope alco lJ sum is often used.

The constant input signal is x(k), each circuit 111.11□, ・
....

The output signal of 11M is q+(k), qz(k),...
+ qM(k), the uniform output signal y (k) is y(k) −x(k)+ΣWi ′ (l i (k)
It can be expressed as (3)-1. Here, q r (k)-Σα1''-x(k-m) (4)-0. Normally, the squared error at the time of data identification determination is often used as the amount for evaluating code amount interference. If the sampling period '1Tc1 data identification determination period is T, the amount of code amount interference is kmodN=.

It can be expressed as However, N=T/Tc (6) and Tc is determined so that equation (6) is an integer. Furthermore, g(k) represents the identification data signal, that is, the estimated amount of the transmission data signal. Maximum slope Arco 8
In the rhythm, a variable is moved in the direction in which the evaluation amount E becomes smaller by an amount proportional to the differential coefficient for that variable.

No selection, weight Wl, W7.・, For wM, kmo
Since dN=0, the maximum slope algorithm becomes kmodN=0. However, Wl(v) represents the value of the voltage weight Wl after the Vth weight update. i, ΔW is a weight update coefficient and must be chosen small enough for the algorithm to converge. Also, e(k) is the error signal, defined as e(k) −y(k) −g(k) (9),
ing.

On the other hand, the weight α1 corresponding to the base of the exponential function. α2゜...
, αM, kmodN=0. Here, . Therefore, the maximum slope algorithm is kmo
dN=0. However, α1(V) represents the value of weight α1 after the Vth weight update, and Δα is an update coefficient of weight αi. Δα also needs to be chosen small enough for the algorithm to converge.

FIG. 4 shows a specific example of the configuration of the control circuit 13. In FIG. 4, 14 is a uniform component, 15 is a cumulative addition circuit that adds values at the time of data identification, 16 is a delay circuit having a delay time corresponding to the weight update period To,
ΔW is the weight Wl,, W2 +.

The update coefficient of wM, Δα, is the weight α1. α2. ..., α2
, and the other symbols have the same meanings as those in FIGS. 1, 2, and 3. First, the weight lol
l, w2.・As for WM, formula (8) is realized using a functional block, but it is practically impossible to perform the cumulative addition of formula (8) from 1 to co. Therefore, in the cumulative addition circuit 15, the weight update period Tc
T inside. It will be added only to 71 Zanzol values. On the other hand, weight α1. α2. ...For 2αM, first, the signal γ+ (k) lγz(k), −,7M
It is necessary to obtain (k). The signal γ1(k) is expressed by the formula (1)
), the unit sample response is α, k−1
It is obtained as the output when the signal X(k)k is input to the circuit. The transfer function of this circuit can be expressed as. On the other hand, since the transfer function of the circuit in the form of Figure 3 is <1/(1-α, z-1) as shown in equation (1), the signal γ1(k) is The signal x(
k) can be obtained as an output signal when inputted.

That is, the signal γ1(k) is the signal q from the terminal 121 to a circuit in which the circuit of the form shown in FIG. 3 and the unit delay circuit are connected in cascade.
This is the output signal when 1(k)' is input. In FIG. 4, the signal γ1(k)'fr is obtained as described above, and the algorithm shown in Nibo is implemented in the same manner as in the case of the weight Wl. However, in this case, a circuit for multiplication by W is required compared to when the weight is Wl.

FIG. 5 shows simulation results of the automatic equalizer according to the first embodiment of the present invention. FIG. 5 shows the solitary wave response, where the dotted line A is the equalizer input signal, the solid line B is the output signal of the equalizer of the embodiment shown in FIG. 2, and the dashed line C is the conventional equalizer shown in FIG. It represents the output signal of the equalizer. Further, the vertical axis is normalized by the peak value to make the effect easier to see, and the horizontal axis is normalized by the data identification period T. Furthermore, in order to make the waveform easier to see, sample points are connected and represented as a continuous signal. The simulation conditions are as shown in Table 1, and from Table 1 and Figure 5, if the automatic equalizer of this embodiment is used, M = 1.
It can be seen that even when the order is small, good equalization performance can be obtained even for subscriber lines that give large distortions and have long tails of solitary waves. This is because the response response of the subscriber line has a strong exponential property9, and therefore the automatic equalizer of this embodiment matches well with the subscriber line.

Regarding the automatic equalizer of this embodiment shown in FIG. 2, the order M=1
In the case of For the conventional automatic equalizer shown in Figure 1, when the order is 3, the equalizer requires 3 additions, 4 multiplications, and 3 unit delays z-1. Comparing the complexity of the equalizer, the one according to this embodiment has a much simpler structure than the one according to the conventional example, but as shown in FIG. It is possible to reduce interference.

Therefore, if the automatic equalizer of this embodiment is used, it is possible to reduce the circuit scale because the order is small, which has the advantage of reducing power consumption and reducing the chip area when integrated into an LSI. There is.

FIG. 6 shows a second embodiment of the automatic equalizer of the present invention. The symbols have the same meanings as those in FIGS. 1 and 2. The automatic equalizer shown in FIG. 6 is the same as the automatic equalizer shown in FIG.
This eliminates the direct path through which signals flow directly to the

In this case as well, when we assume that αl<α2 . The same effect as an automatic equalizer can be obtained. In this case, the control circuit 13 is not affected in any way, and the configuration shown in FIG. 4 can be used.

(Effects of the Invention) The present invention is an automatic equalizer with a dinotal signal processing configuration configured by a linear sum of circuits having one or more exponential unit sample responses, and has good matching with subscriber lines.
It has the advantage that good equalization characteristics can be obtained with a small order. Therefore, the circuit size can be reduced, power consumption can be reduced,
It is possible to reduce the chip area when integrated into an LSI.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional automatic equalizer, FIG. 2 is a block diagram of an embodiment of the automatic equalizer of the present invention, and FIG. 3 is a concrete diagram of a circuit having an exponential unit sample response. configuration diagram, 4th
5 is a diagram showing the simulation results showing the effect of the automatic equalizer of the present invention. FIG. 6 is a diagram of the configuration of a second embodiment of the automatic equalizer of the present invention. It is. 1: Analog signal input terminal, 2: Analog-to-digital conversion circuit, 3: Equal input terminal, 4: Delay circuit, 5: Multiplier circuit, 6 Two-addition circuit, 7: Equal output terminal, 8: Data identification judgment circuit , 9: identification data output terminal, 1θ: weight control circuit, 111 + 112+..., 11M: unit sample response α, α2k, respectively.・Circuit with −2θMk, 121+122 H・,
12M: Output terminal, 13: Control circuit, 14: Equalizer, 1
5 cumulative addition circuit, 16: delay circuit, WO+ Wi +
W2 +..., wM: weight, αl, α2. ..., αM
Weight corresponding to the base of the biexponential function, k: sample time variable, qll(121...+qM: signal, ΔW: weight update coefficient, Δα: weight update coefficient, To duality update period, Tc:
Sampling period, T: data identification judgment period. Procedural amendment export) 1. Indication of the case 1982 Patent Application No. 209962 2, Name of the invention Automatic equalizer 3, Person making the amendment Relationship to the case Patent applicant office (105) 1-7-12 Toranomon, Minato-ku, Tokyo
No. 4 Agent Residence PJT (105) No. 6, 12-7 Ko, Toranomon, Minato-ku, Tokyo Contents of amendment (1) The statement “obtains equivalence” on page 4, line 41 of the specification. Correct it to "obtain equalization performance." (3) Ibid., page 9] Line 1: ``・You need to choose.''
Insert the following sentence after. “Also, in order for the 7-stem to be stable, O≦α1≦1
It is necessary to control α1 under the following conditions. ” (4) On page 14, lines 5 to 6 of the same book, “α1〈α
2〈...〈αM... of exponential function'' is changed to ``
When it is assumed that α1〉α2〉...〉αM, it is corrected to be the largest, that is, the closest exponential function.

Claims (2)

[Claims] (1) Consists of a circuit having an exponential unit sample response and a multiplication circuit that changes the size by multiplying the output of the circuit by a weight, and provides the base of the exponential function of the circuit having the exponential unit sample response. An automatic equalizer, characterized in that it controls the amount and said weights. (2) one or more circuit networks consisting of a circuit having an exponential unit sample response and a multiplication circuit that changes the size by multiplying the output of the circuit by a full weight, and each of the one or more circuit networks; It is constituted by an adder circuit that adds the output and the input of the automatic equalizer, or an adder circuit that adds only each output of the plurality of circuit networks, and provides the base of the exponential function of the circuit having the exponential unit sample response. An automatic equalizer, characterized in that it controls the amount and said weights.