JPS60101954A - Ic package and manufacture thereof - Google Patents
Ic package and manufacture thereofInfo
- Publication number
- JPS60101954A JPS60101954A JP20929283A JP20929283A JPS60101954A JP S60101954 A JPS60101954 A JP S60101954A JP 20929283 A JP20929283 A JP 20929283A JP 20929283 A JP20929283 A JP 20929283A JP S60101954 A JPS60101954 A JP S60101954A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- lead
- chip
- frame
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49558—Insulating layers on lead frames, e.g. bridging members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明ｉｍ、Ｊ： Ｉ Ｏなどのパッケージおよびその
製法に関するものＣある。DETAILED DESCRIPTION OF THE INVENTION The present invention im, J: relates to a package such as IO and a method for producing the same.
従来、Ｄ工ｐ ＱＵ、やフラットパッケージ型のＩＣパ
ッケージは、リードフレーム’ｋＵめ込み、トランスフ
ァモールド成形全行なう成型用の金型が必要であり、コ
ストアップの原因となっていた、本発明げ成形用の金型
全必要とせず、コストダウンを達成できるＩＣなどのパ
ッケージおよびその製法を提供すゐこと全目的とする。Conventionally, D-process pQU and flat package type IC packages require a mold for inserting the lead frame and performing transfer molding, which increases costs. The overall purpose is to provide a package such as an IC that does not require a mold for molding and can achieve cost reduction, and a manufacturing method thereof.
以下本発明の一実施例をその製造工程に従って説明する
。第１図において、１はリードフレームであり、０．２
鴫程度の厚さのリン育鋼板や４２−アロイなどから形成
され、外筒枠部１ａ、リード部１ｂ・・・・・・、チッ
プ取付部１０などが設けである、リードフレーム１ｒＪ
プレスやエツチングなどにてこの状態ではリード部１ｂ
・・・・・・は先端０Ｉ１１が軽く湾曲可能である。つ
ぎに第２図に示すように、り一ドフンーム１の下面に樹
１１旨１ｍ ２ ｋ密着して設ける。An embodiment of the present invention will be described below according to its manufacturing process. In Fig. 1, 1 is a lead frame, and 0.2
A lead frame 1rJ is formed from a phosphorus-brown steel plate or 42-alloy with a thickness of about 100 ml, and is provided with an outer cylinder frame portion 1a, a lead portion 1b, a chip mounting portion 10, etc.
In this state, lead part 1b is removed by pressing, etching, etc.
. . . tip 0I11 can be slightly bent. Next, as shown in FIG. 2, a tree 11 is installed in close contact with the lower surface of the dome 1 for a distance of 1 m 2 k.
この樹脂層２はエポキシ樹脂外ど會ａ２〜０．４咽程度
の厚さに形成したものである一本実施例でげガラスなど
の平滑な合板上に離型剤？塗布し、その而に多数個取り
のリードフレームの中心に合わせて印刷により樹脂層全
多数個形成し、こルらの樹脂層に合わせてリードフレー
ムを置き、加熱して樹脂層を半キュアーあるいは完全キ
ュアーの状態とし、リードフレームに樹脂層を密着して
いる。This resin layer 2 is formed of an epoxy resin with a thickness of about 2 to 0.4 mm.In this embodiment, a mold release agent is applied on a smooth plywood such as glass. After that, a large number of resin layers are formed by printing in alignment with the center of a multi-piece lead frame, the lead frame is placed in alignment with these resin layers, and the resin layer is semi-cured or cured by heating. It is in a completely cured state and the resin layer is tightly attached to the lead frame.
冷却すると樹Ｉｔ！ ）＠は離型剤により合板から容易
に分離できるのである、このようにして第２図示のよう
にリードフレーム１０丁面に樹脂層２葡密着して設けた
あと、第３図示のようにチップ取付部１Ｃ上に工（！Ｘ
ＬＳＩなどのチップ３金固廚し、各リード部とワイヤ
ボンディングにより＃、続さｎる。このワイヤボンディ
ングのとき、各リード部１′ｂ・・・・・・の先端に樹
脂層２により固定されているのでリード部の押え板がな
くてもリード部が持上がることがなく樹１１旨層２ヶ真
空チャックするだけで効惠よくワイヤボンティングでき
る、またり−トフレーム１が多数個取りの場合、ワイヤ
ボンディングの前に１つづつ分割し第２図示の状別にし
ておくと、アルミ線のワイヤボンティングできる。When it cools down, it grows! )@ can be easily separated from the plywood using a mold release agent.In this way, two resin layers are closely attached to the lead frame 10 as shown in the second figure, and then the chips are separated as shown in the third figure. Machining on the mounting part 1C (!X
A chip such as an LSI is fixed with gold and connected to each lead part by wire bonding. During this wire bonding, since the ends of each lead part 1'b are fixed by the resin layer 2, the lead part does not lift up even if there is no holding plate for the lead part, and the tree 11 is fixed. Wire bonding can be performed efficiently by simply vacuum-chucking two layers. If the frame 1 has multiple pieces, it is best to separate them one by one and separate them into the shapes shown in the second figure before wire bonding. Wire bonding of aluminum wire is possible.
このあと第４図示のように、リードフレーム１の上面に
モールド拐４を密着し、ＩＣなどのチップ３を封止する
、本実施例ではモールド材４もエポキシ樹１１旨から喰
成され、樹脂層２と各リード部の間隙より密着してチッ
プ３金気密状聾に封止する、モールド材４に樹脂Ｊｆ１
２より小形に形成され、樹脂層２の外周に広がらないよ
うに形成される、このあと第５図示のようＶこリードフ
レーム１の外枠部１ａが切断され、リード部１１）’ｚ
折曲けて先端を樹脂層２より下方に位置させ、ＩＣパッ
ケージ互が完成する、
このようにして形成されたＩＣパッケージ５はリードフ
レーム１の下方の樹脂層２と、リードフレーム１の上方
のモールド材４とによりチップ３を封止してい；ｂＰそ
してチップ３全封止する樹脂層２およびモールド材４は
成型用金型々してリードフレーム１０丁面することがで
きる、このため製造が容易で安価なＩＣパッケージが可
能となる。Thereafter, as shown in the fourth diagram, a mold material 4 is closely attached to the upper surface of the lead frame 1 to seal a chip 3 such as an IC. In this embodiment, the mold material 4 is also made of epoxy tree 11 and resin Resin Jf1 is applied to the molding material 4 to tightly seal the chip 3 in a gold-tight manner through the gaps between the layer 2 and each lead.
The outer frame portion 1a of the V-shaped lead frame 1 is then cut as shown in FIG.
The IC package 5 formed in this way has the resin layer 2 below the lead frame 1 and the resin layer 2 above the lead frame 1. The chip 3 is sealed with a molding material 4; bP, and the resin layer 2 and the molding material 4 that completely seal the chip 3 can be molded together with the lead frame 10, which makes the manufacturing process easier. Easy and inexpensive IC packaging becomes possible.
なお本実施例では樹脂層２とモールド４′Ａ４は同じエ
ポキシ樹Ｉｌｌ用いたが、別のもの音用いてもよい。In this embodiment, the same epoxy resin is used for the resin layer 2 and the mold 4'A4, but different materials may be used.
つぎにリードフレーム１の下部に密着さｎる樹ｌ旨層２
の他の製法について説明する。まずリードフレーム１全
表裏反対にして加熱されたホットプレート上に載置する
、ホットプレートの温度は樹脂層２にエポキシ樹脂を用
いる場合、この樹脂のキュア一温度（約１５０度Ｃ）以
下でこの樹脂の軟化温度（約６０１現Ｃ）以上に保たれ
、本例でに約７０度Ｃに設定されている、そしてリード
フレーム１のチップ取付部ＩＣＥ対応させてペレット状
の正方形状のｖＡｌ旨１１！ ２ ’に載置し、上方よ
り加圧してリードフレーム１に樹脂層２を仮止めする。Next, the wood layer 2 is tightly attached to the bottom of the lead frame 1.
Another manufacturing method will be explained. First, place the lead frame 1 completely upside down on a heated hot plate. If an epoxy resin is used for the resin layer 2, the temperature of the hot plate is below the curing temperature of this resin (approximately 150 degrees Celsius). It is maintained above the softening temperature of the resin (approximately 601 degrees Celsius), which is set at approximately 70 degrees Celsius in this example, and a pellet-like square vAl material 11 is formed in correspondence with the chip attachment part ICE of the lead frame 1. ! 2' and pressure is applied from above to temporarily fix the resin layer 2 to the lead frame 1.
このあと樹脂層２が落込むような穴會設けた支持板上に
リードフレームを反転させてｇ置し、加熱して樹脂）ａ
２ ’に半キュアーあるいは完全キュアーの状態にし
てリードフレーム１に樹）１８層２を密シ１９させゐ、
この状７１１４では各リード部１ｂ・・・・・・の間の
部分に樹１１ｍ１１２の樹）芦が入り込んで確実に固定
される。この後の工程は前記実施例と同様に行えばよい
、この場片側ｉ前層の厚さに０．５〜１咽が適当である
。また樹脂層はガラス繊維を混入したものでもよい。After this, the lead frame is inverted and placed on a support plate with a hole in which the resin layer 2 falls, and heated to make the resin)
2', in a semi-cured or fully cured state, and tightly seal layer 2 (18) on lead frame 1,
In this state 7114, the reeds of the trees 11m and 112 enter the portions between the respective lead portions 1b, and are securely fixed. The subsequent steps may be carried out in the same manner as in the previous embodiment. In this case, the thickness of the front layer on one side is preferably 0.5 to 1 mm. The resin layer may also contain glass fibers.
以上述べたように本発明によれば、ＩＣなどのパッケー
ジが成型用金型なしで形成できるためコストダウンでき
、特に少量多品種の場合最適である、またワイヤボンド
などが容易に行なえ、製造が極めて容品であ／）。As described above, according to the present invention, a package such as an IC can be formed without a molding die, resulting in cost reduction, which is especially suitable for small-lot, high-mix production.In addition, wire bonding can be easily performed, making manufacturing easier. Very classy/).
図面は不発明の一実施例の＃造工８全示し、第１Ａ図は
リードフレームの正面図、第１Ｂ図はその中央縦断面図
、第２Ａ図は樹脂層全役けたリードフレームの正面図、
第２Ｂ図にその右側面図、第３Ａ図にチップを固腐し接
続したリードフレームの正面図、第３Ｂ図にその右側面
図、ＭｊＡ図はモールド材を設けたリードフレームの正
面図、第４Ｂ図はその右側面図、第５Ａ図ｉＩＣパッケ
ージの正面図、第５Ｂ図はその右＋ｔＵ＋面図である。
１・・・リードフレーム
２・・・樹＋１旨層
３・・・チップ
４・・・モールド材
５・・・ＩＣパッケージ、
以 上
特許出願人 株式会社 梢工舎The drawings show the entire structure #8 of an embodiment of the invention, FIG. 1A is a front view of the lead frame, FIG. 1B is a longitudinal cross-sectional view of the center thereof, and FIG. 2A is a front view of the lead frame with the resin layer fully exposed. ,
Fig. 2B is a right side view of the lead frame, Fig. 3A is a front view of the lead frame to which the chip is solidified and connected, Fig. 3B is its right side view, and Fig. MjA is a front view of the lead frame with the molding material provided. 4B is a right side view thereof, FIG. 5A is a front view of the iIC package, and FIG. 5B is a right +tU+ side view thereof. 1...Lead frame 2...Tree + 1 layer 3...Chip 4...Mold material 5...IC package Patent applicant Kozue Kosha Co., Ltd.
Claims (1)
、上記リードフレームの上面に固着され各リード部と接
続されたＩＣなどのチップと、上記リードフレームの上
面に密着され上記チップを被覆し上記樹１１旨層と上記
リードフレームの間隙より密着されるモールド材とを設
けたＩＣなどのパッケージ。 （２）リードフレームの下面に樹脂層を密着形成し、上
記リードフレームの上面にＩＣなどのチップ全同着し、
上記チップと上記リードフレームの各リードとを接続し
たあと、上記リードフレームの上面において上記チップ
葡モールド材にて被覆し、上記樹ｉ旨層と上記モールド
材と金上記リードることを特徴とする工Ｃチップなどの
パッケージの製法−[Claims] (]) A resin layer provided in close contact with the lower surface of the lead frame, a chip such as an IC fixed on the upper surface of the lead frame and connected to each lead part, and a resin layer provided on the upper surface of the lead frame. A package such as an IC, which is provided with a molding material which is closely attached to cover the chip and is closely attached through the gap between the resin layer and the lead frame. (2) A resin layer is closely formed on the bottom surface of the lead frame, and all chips such as ICs are attached to the top surface of the lead frame,
After the chip and each lead of the lead frame are connected, the top surface of the lead frame is covered with the chip molding material, and the wood layer, the molding material, and the gold lead are connected. Manufacturing method for packages such as engineering C chips
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20929283A JPS60101954A (en) | 1983-11-08 | 1983-11-08 | Ic package and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20929283A JPS60101954A (en) | 1983-11-08 | 1983-11-08 | Ic package and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60101954A true JPS60101954A (en) | 1985-06-06 |
Family
ID=16570524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20929283A Pending JPS60101954A (en) | 1983-11-08 | 1983-11-08 | Ic package and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60101954A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5487181A (en) * | 1977-12-23 | 1979-07-11 | Hitachi Ltd | Resin sealing method for semiconductor element |
-
1983
- 1983-11-08 JP JP20929283A patent/JPS60101954A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5487181A (en) * | 1977-12-23 | 1979-07-11 | Hitachi Ltd | Resin sealing method for semiconductor element |
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