JPS6473631A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS6473631A JPS6473631A JP62231604A JP23160487A JPS6473631A JP S6473631 A JPS6473631 A JP S6473631A JP 62231604 A JP62231604 A JP 62231604A JP 23160487 A JP23160487 A JP 23160487A JP S6473631 A JPS6473631 A JP S6473631A
- Authority
- JP
- Japan
- Prior art keywords
- probe
- terminal
- probes
- positioning
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
PURPOSE:To provide good contact with probes by so providing a positioning terminal in contact with a probe separately from a terminal as to accurately bring a probe for an electric test into contact with an input/output terminal and power supply terminal. CONSTITUTION:A terminal 11 for input/output signal and supplying power source and positioning terminals 13, 14, 15, 16 of probes 12 provided at the four corners of an LSI chip 10 are provided on an LSI chip 10. Here, first, second, third and fourth positioning probes 23, 24, 25, 26 corresponding to the terminals 13, 14, 15, 16 are prepared. In case of an electric test for an LSI, an open monitor 17 is connected from the probe 23 to the probe 26, and the probes 24, 25 are directly shortcircuited. In this case, a closed loop of the probe 23, a buried layer 21, the probe 24, the probe 25, a buried layer 22, and the probe 26 is formed through the monitor 17.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62231604A JPH06105733B2 (en) | 1987-09-14 | 1987-09-14 | Integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62231604A JPH06105733B2 (en) | 1987-09-14 | 1987-09-14 | Integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6473631A true JPS6473631A (en) | 1989-03-17 |
JPH06105733B2 JPH06105733B2 (en) | 1994-12-21 |
Family
ID=16926115
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62231604A Expired - Lifetime JPH06105733B2 (en) | 1987-09-14 | 1987-09-14 | Integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06105733B2 (en) |
-
1987
- 1987-09-14 JP JP62231604A patent/JPH06105733B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH06105733B2 (en) | 1994-12-21 |
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