JPH06105733B2 - Integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly to a positioning structure for a probe and a substrate terminal used when testing an integrated circuit substrate at a semiconductor wafer stage.

[Conventional technology]

A so-called LSI tester is used when performing an electrical test of an integrated circuit chip (hereinafter referred to as an LSI) at a semiconductor wafer stage. The electrical test in the LSI tester is performed by supplying a signal and power according to the test content from the probe of the tester to the signal terminal and power supply terminal of the LSI. Conventionally, when testing this type of LSI, it was necessary to visually position all the terminals of the LSI between the probe and the center of the LSI terminal prior to the test.

[Problems to be solved by the invention]

The above-mentioned conventional LSI is a combination of the probe and the LSI during the electrical test of the LSI.
There is a drawback in that a great amount of labor is required to accurately position the terminals.

The object of the present invention is to solve the above-mentioned drawbacks and to provide a probe for a tester.
An object of the present invention is to provide an integrated circuit device capable of accurately contacting an LSI terminal.

[Means for solving problems]

The integrated circuit device of the present invention is configured such that the probe contacts the input / output terminal and the power supply terminal provided on the main surface of the semiconductor chip, separately from the terminal so that the probing probe for electrical test accurately contacts. It is characterized in that a positioning terminal is provided in contact therewith.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing an integrated circuit device according to an embodiment of the present invention. In the figure, the integrated circuit device of this embodiment is
Terminal 11 that supplies I / O signals and power on I-chip 10
(This terminal 11 is supplied with a test signal from a test device such as an LSI tester from a probe 12) and positioning terminals 13, 14, 15, 16 of the probe 12 provided at four corners of the LSI chip 10. ,
Composed. Here, the first, second, third and fourth positioning probes 23, 24, 25 and 26 corresponding to the positioning terminals 13, 14, 15 and 16 are prepared. Now, in the LSI electrical test, the open monitor 17 is connected between the first positioning probe 23 and the fourth positioning probe 26, and the second and third positioning probes 24, 25 are Make a direct short-circuit connection externally.

FIG. 2 is a sectional view of the LSI chip 10 of FIG. In the same figure, the connection between the positioning terminals 13, 14, 15, 16 in FIG. 1 is shown in the chip 10 and in the chip 10. In FIG. 2, the numbers of the positioning terminal and the probe correspond to those in FIG. 1 and are the same. This figure assumes an LSI having an oxide film isolation structure, and on the p-type substrate 20, n-type buried layers 21, 22, an oxide film 23, a positioning terminal 13,
14, 15 and 16 are formed. Here, in order to reverse bias the PN junction formed by the p-type substrate 20 and the buried layers 21 and 22, in this example, the V _SUB potential, the buried layer 21 and the buried layer 21
GND potential is applied to 22 (V _SUB <GND potential). FIG. 2 shows that the positioning probes 23, 24, 25, 26 have positioning terminals 13, 14, 15,
It shows the case where all 16 are exactly matched. In this case, a closed loop of the positioning probe 23 → embedded layer 21 → positioning probe 24 → positioning probe 25 → embedded layer 22 → positioning probe 26 is configured via the open monitor 17. Since the buried layers 21 and 22 generally have low resistance values, the resistance value between the probes 23 and 26 shows a low value. Next, if at least one of the positioning probes 23, 24, 25, 26 is out of the positioning terminals 13, 14, 15, 16 then each probe 12 is not connected to each terminal 11. This means that a part of the position between the positioning probes is in an open state, so the measured value of the open monitor 17 shows a very large value or infinity. This measured value can be easily detected by the monitor 17.

〔The invention's effect〕

As described above, according to the present invention, when the test probe is positioned on the input / output terminal and the power supply terminal at the time of testing the LSI, the positioning probe is provided on the positioning terminal provided separately from the input / output and the power supply terminal. Accurate alignment with an external monitor has the effect of enabling accurate and easy positioning of the entire probe with respect to the terminals.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing an integrated circuit device of one embodiment of the present invention, and FIG. 2 is a sectional view showing the semiconductor chip of FIG. 10 …… LSI chip, 11 …… I / O and power supply terminals, 12…
… Test probe, 13,14,15,16 …… Positioning terminal, 17…
… Open monitor, 23,24,25,26 …… Positioning probe, 20
...... P-type substrate, 21,22 …… N-type buried layer, 23 …… Oxide film.

Claims (1)

[Claims] 1. A positioning terminal for the probe is provided separately from the terminals so that the probing probe for electrical test can accurately contact the input / output terminal and the power supply terminal provided on the main surface of the semiconductor chip. An integrated circuit device characterized by the above.