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JPS6440892A - Pattern generator - Google Patents

Pattern generator

Info

Publication number
JPS6440892A
JPS6440892A JP62196666A JP19666687A JPS6440892A JP S6440892 A JPS6440892 A JP S6440892A JP 62196666 A JP62196666 A JP 62196666A JP 19666687 A JP19666687 A JP 19666687A JP S6440892 A JPS6440892 A JP S6440892A
Authority
JP
Japan
Prior art keywords
dot
outputted
data
inputted
shift register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62196666A
Other languages
Japanese (ja)
Other versions
JP2570755B2 (en
Inventor
Nobumasa Ozeki
Masayuki Matsubayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Brother Industries Ltd
Original Assignee
Brother Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Brother Industries Ltd filed Critical Brother Industries Ltd
Priority to JP62196666A priority Critical patent/JP2570755B2/en
Publication of JPS6440892A publication Critical patent/JPS6440892A/en
Application granted granted Critical
Publication of JP2570755B2 publication Critical patent/JP2570755B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Controls And Circuits For Display Device (AREA)

Abstract

PURPOSE: To simplify the constitution of a device by providing a means for inserting a displaying dot between adjacently outputted dot data of font when an identifying dot of the dot data and a dot in the endmost column are together displaying dots. CONSTITUTION: Dot data at the right endmost and the left endmost of fonts outputted from a character generator ROM 2 are inputted to a graphic character identifying circuit 7, when dots at both ends of the same raster are displaying dots, an identifying signal '1' is outputted, latched to a latched circuit 8 synchronized with a latch signal LT having the same period as a shift register loading signal-LOAD and inputted to the least significant digit of a shift register 5. The data inputted to the shift register 5 are outputted as a serial video signal SQ in order from dot data in the most significant digit to the operational data S1 in the least significant digit.
JP62196666A 1987-08-06 1987-08-06 Pattern generator Expired - Lifetime JP2570755B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62196666A JP2570755B2 (en) 1987-08-06 1987-08-06 Pattern generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62196666A JP2570755B2 (en) 1987-08-06 1987-08-06 Pattern generator

Publications (2)

Publication Number Publication Date
JPS6440892A true JPS6440892A (en) 1989-02-13
JP2570755B2 JP2570755B2 (en) 1997-01-16

Family

ID=16361573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62196666A Expired - Lifetime JP2570755B2 (en) 1987-08-06 1987-08-06 Pattern generator

Country Status (1)

Country Link
JP (1) JP2570755B2 (en)

Also Published As

Publication number Publication date
JP2570755B2 (en) 1997-01-16

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