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JPS6430271A - Manufacture of insulated-gate semiconductor device - Google Patents

Manufacture of insulated-gate semiconductor device

Info

Publication number
JPS6430271A
JPS6430271A JP18639787A JP18639787A JPS6430271A JP S6430271 A JPS6430271 A JP S6430271A JP 18639787 A JP18639787 A JP 18639787A JP 18639787 A JP18639787 A JP 18639787A JP S6430271 A JPS6430271 A JP S6430271A
Authority
JP
Japan
Prior art keywords
film
trench
silicon
polycrystalline silicon
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18639787A
Other languages
Japanese (ja)
Inventor
Tetsuo Izawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18639787A priority Critical patent/JPS6430271A/en
Publication of JPS6430271A publication Critical patent/JPS6430271A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To achieve a good controllability by a method wherein sidewalls are formed in a trench and an impurity is directly introduced into a semiconductor layer through the regions from which the sidewalls are removed to form low impurity concentration layers. CONSTITUTION:A silicon oxide film 21 is formed on the surface of a semiconductor substrate 20 and, after a trench 23 is formed, a silicon nitride film 22 is formed. Then a silicon oxide film 24 is formed and, successively, the silicon oxide films 24a left on the side surfaces of the trench 23. After a polycrystalline silicon film 25 is deposited, the polycrystalline silicon film 25a is left. Then arsenic ions are implanted to form low impurity concentration regions 26. Then the polycrystalline silicon film 25a is etched off and, successively, the silicon nitride film 22 is removed. A trench 27 is formed and a gate oxide film 28 is formed on the exposed silicon layer. Then a polycrystalline silicon film 29 is deposited over the whole surface and the polycrystalline silicon film 29a is left in the trench 27. Then the silicon oxide film 21 is etched off and arsenic ions are implanted to form electrodes 301 and 302.
JP18639787A 1987-07-24 1987-07-24 Manufacture of insulated-gate semiconductor device Pending JPS6430271A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18639787A JPS6430271A (en) 1987-07-24 1987-07-24 Manufacture of insulated-gate semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18639787A JPS6430271A (en) 1987-07-24 1987-07-24 Manufacture of insulated-gate semiconductor device

Publications (1)

Publication Number Publication Date
JPS6430271A true JPS6430271A (en) 1989-02-01

Family

ID=16187684

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18639787A Pending JPS6430271A (en) 1987-07-24 1987-07-24 Manufacture of insulated-gate semiconductor device

Country Status (1)

Country Link
JP (1) JPS6430271A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5472903A (en) * 1994-05-24 1995-12-05 United Microelectronics Corp. Isolation technology for sub-micron devices
JPH08501015A (en) * 1993-11-03 1996-02-06 ターゲット セラピュウティクス,インコーポレイテッド Electrolytically separable joints for endovascular embolization devices
JPH09321278A (en) * 1995-12-28 1997-12-12 Lg Semicon Co Ltd Manufacture of mos electric field-effect transistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08501015A (en) * 1993-11-03 1996-02-06 ターゲット セラピュウティクス,インコーポレイテッド Electrolytically separable joints for endovascular embolization devices
US5472903A (en) * 1994-05-24 1995-12-05 United Microelectronics Corp. Isolation technology for sub-micron devices
JPH09321278A (en) * 1995-12-28 1997-12-12 Lg Semicon Co Ltd Manufacture of mos electric field-effect transistor

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