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JPS5977231U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5977231U
JPS5977231U JP17373582U JP17373582U JPS5977231U JP S5977231 U JPS5977231 U JP S5977231U JP 17373582 U JP17373582 U JP 17373582U JP 17373582 U JP17373582 U JP 17373582U JP S5977231 U JPS5977231 U JP S5977231U
Authority
JP
Japan
Prior art keywords
semiconductor element
insulating substrate
area
wiring pattern
lid member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17373582U
Other languages
English (en)
Other versions
JPS635237Y2 (ja
Inventor
寺澤　正已
Original Assignee
京セラ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京セラ株式会社 filed Critical 京セラ株式会社
Priority to JP17373582U priority Critical patent/JPS5977231U/ja
Publication of JPS5977231U publication Critical patent/JPS5977231U/ja
Application granted granted Critical
Publication of JPS635237Y2 publication Critical patent/JPS635237Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は薄膜生成技術の配線パターンを有した半導体装
置の、従来の封着方法を示す断面図、第２図は本考梁半
導体装置を示す断面図、また第３図は本考案の変形態様
を示した要部拡大断面図である。 ２・・・半導体素子、４．２０・・・ポンディングパッ
ド、５・・・配線パターン、６・・・絶縁保護層、７・
・・配線パターン領域、１０・・・ボンディングワイヤ
、１１．１５・・・キャップ、１６・・・封着部、１７
゜２２・・・導電路、１８Ａ、１８Ｂ、２３・・・スル
ーホール導電体、１９．２４・・・導体パターン。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体素子が搭載された領域、及び薄膜生成技術及びエ
    ツチング技術に依り形成された配線パターン領域を有す
    る絶縁基板と、該半導体素子搭載領域を気密封止する蓋
    部材とから構成され、前記蓋部材は前言巨半導体素子搭
    載領域と前記配線パターン領域を区分するように絶縁基
    板上に封着され、且つ前記封着部の下方の絶縁基板内に
    設けられた導電路を介して前記半導体素子と前記配線パ
    ターンとが接続して成ることを特徴とする半導体装置。
JP17373582U 1982-11-16 1982-11-16 半導体装置 Granted JPS5977231U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17373582U JPS5977231U (ja) 1982-11-16 1982-11-16 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17373582U JPS5977231U (ja) 1982-11-16 1982-11-16 半導体装置

Publications (2)

Publication Number Publication Date
JPS5977231U true JPS5977231U (ja) 1984-05-25
JPS635237Y2 JPS635237Y2 (ja) 1988-02-12

Family

ID=30378401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17373582U Granted JPS5977231U (ja) 1982-11-16 1982-11-16 半導体装置

Country Status (1)

Country Link
JP (1) JPS5977231U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61154152A (ja) * 1984-12-21 1986-07-12 フィリップス　エレクトロニクス　ネムローゼ　フェンノートシャップ 電子装置用ハウジング

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5413966A (en) * 1977-07-01 1979-02-01 Nippon Electric Co Substrate for multiilayer wiring
JPS5471572A (en) * 1977-11-18 1979-06-08 Fujitsu Ltd Semiconductor device
JPS5731165A (en) * 1980-07-31 1982-02-19 Fujitsu Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5413966A (en) * 1977-07-01 1979-02-01 Nippon Electric Co Substrate for multiilayer wiring
JPS5471572A (en) * 1977-11-18 1979-06-08 Fujitsu Ltd Semiconductor device
JPS5731165A (en) * 1980-07-31 1982-02-19 Fujitsu Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61154152A (ja) * 1984-12-21 1986-07-12 フィリップス　エレクトロニクス　ネムローゼ　フェンノートシャップ 電子装置用ハウジング

Also Published As

Publication number Publication date
JPS635237Y2 (ja) 1988-02-12

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