JPS5932025A - Bidirectional bus extending system - Google Patents

Abstract

PURPOSE:To have flexible correspondence to an extension of an address space due to an increase of peripheral devices, by providing settable upper and lower addresses by a program given from a CPU. CONSTITUTION:A CPU15 is connected to peripheral devices such as an input device I/O and a bidirectional bus extending device 10 via a common bus 16. The device 10 consists of an upper limit address register 21, a lower limit address register 22, an upper limit address comparator 23, a lower limit address comparator 24, and an OR gate 25. The registers 21 and 22 can be set freely from the CPU15 by a program via a common bus. When the addresses contained between the addresses set at both registers 21 and 22 are designated through an address bus, an extended common bus 17 is electrically connected to the CPU15 to control a peripheral device corresponding to a designated address. Then the data is transmitted and received.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a bidirectional bus expansion system in microprocessor systems and the like.

(2) Background of the technology In general, in microprocessor systems, the central processing unit (CPU) is connected to peripheral devices, such as input/output devices (Ilo) and memory devices, through a common bus. data can be sent and received, and peripheral devices can be controlled from the CPU. The common bus includes three types of buses: an address bus, a control bus, and a data bus. When adding one peripheral device to the above system, the common bus is extended and the peripheral device is connected. The common bus is a bidirectional bus, the extension of which is via a bus amplifier.

The bus amplifier consists of a plurality of bidirectional amplifiers (transceivers) consisting of two three-state drivers that are switched to either a high impedance state or an enabled state by a control signal.Address of peripheral devices to be expanded The transceiver must be in a high impedance state when an address for the extended address space is not generated, and must be enabled when a valid address for that address space is generated. Transceiver control has become an important issue when expanding bidirectional buses.

(3) Prior Art and Problems Conventionally, bus amplifiers or transceivers used for extending the above-mentioned common bus have been controlled.

A circuit as shown in FIG. 1 is used.

In FIG. 1, the 0PU 15 is connected to an expanded common bus 17 via a common bus 16 and a transceiver 11. The address setting switches 13 are manually set, and the number of switches is determined for the amount of address space. The address comparator 12 compares the address of the expanded peripheral device 14 set in the address setting switch 13 with an address specifying a peripheral device to be connected via an address bus included in the common bus 16. 1. When both match, a low level output signal plane is generated at the output terminal, and the transceiver 11 is enabled.

As described above, the 0PU 15 and the peripheral device 14 become capable of transmitting and receiving data to each other, and the bidirectional bus is expanded. Transceiver 11 is comprised of a plurality of amplifiers 31 and AND gates 32 and 33 as shown in FIG. The input/output lines DBO to DB3 are connected to the common bus 16, and the input lines DIO to DI3 and the output lines R00 to R00 are connected to the common bus 16.
3 is connected to the expanded common bus. Signal R specifies the direction of transmission of the transceiver.

However, in the circuit that expands the bidirectional bus mentioned above, the address space of the peripheral device to be expanded must be manually set using an address setting switch when adding a device, and it is difficult to manage the address space of the expansion side flexibly. I had a problem with this point.

(4) Object of the Invention The object of the present invention is to provide an upper limit address register and a lower limit address register, and to set the registers by a program from the CPU, in view of the problems in the conventional circuit described above. The purpose is to manage the address space by a program and to be able to respond flexibly to expansion of the address space.

(5) Structure of the Invention In the present invention, in a bidirectional bus expansion method in which a microprocessor and a peripheral device are connected via a bus amplifier, an upper limit address register that sets the upper limit value of the address space of the peripheral device to be expanded; a lower limit address register that sets the lower limit value of the address space; an upper limit address comparator that compares an address signal from the microprocessor specifying the peripheral device with the address set in the upper limit address register; It is equipped with a lower limit address comparator that compares an address signal specifying a peripheral device with an address set in the lower limit address register, and sets the upper limit address register and the lower limit address register according to a command from the microprocessor. When the address of the peripheral device specified from is between the upper limit value set in the upper limit address register and the lower limit value set in the lower limit address register,
A bidirectional bus expansion method is provided in which the bus amplifier serving as an expansion point is enabled to transmit and receive data.

(6) Embodiment of the Invention A block circuit diagram of a device implementing a bidirectional bus expansion method as an embodiment of the present invention is shown in FIG. In the figures, elements that are the same as those shown in FIG. 1 are given the same reference numerals.

The 0PU 15 is connected to peripheral devices, such as input/output devices I10, via a common bus 16, which is connected to a bus amplifier, or transceiver 11, of the bidirectional bus expansion device 10. In addition to the transceiver 11, the device 10 includes an upper limit address register 21°, a lower limit address register 22. Upper limit address comparator 23. Lower limit address comparator 24. and an or gate 25. Upper limit address register 2
1 and the input terminal of the 1 limit address register 220 are connected to the data bus in the common bus 16, the output of the upper limit address register 21 is sent to the upper limit address comparator 23, and the output of the lower limit address register 22 is sent to the lower limit address comparator. 24. Upper limit address comparator 23
In addition to the common bus 1, the lower limit address comparator 24
Inputs are provided from the address bus at 6. Output of upper limit address comparator 23 and lower limit address comparator 24
The outputs of are applied to the first and second inputs of OR gate 25, respectively. The output of the OR gate 25 is a plane signal that enables the transceiver 11 when it is at a low level, and puts the transceiver 11 into a high impedance state when it is at a high level. The /W signal is a signal that indicates the direction of the transceiver.

If the above-mentioned device is used, the upper limit address register 21 and the lower limit address register 22 can be freely set by a program from the 0PU 15 via the data bus, and the upper limit address register 21 and the lower limit address register 2 can be set freely by the program.
When an address included between the addresses set in 2 is specified through the address bus, the extended common bus 17 is electrically connected to 0PU 15 & the peripheral device corresponding to the specified address is controlled. or send and receive data.

(7) Effects of the Invention According to the present invention, the upper limit address and lower limit address of the address space to be expanded can be set by a program from the CPU, and it is possible to flexibly respond to expansion of the address space due to the addition of peripheral devices, etc. can.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of a circuit that performs conventional bidirectional bus expansion, FIG. 2 is a block circuit diagram of a device that performs a bidirectional bus expansion method as an embodiment of the present invention, and FIG. FIG. 10... Bidirectional bus expansion device, 11... Transceiver. 12...Address comparator. 13... Stress setting switch. 14...Extended peripheral device. 15...OPU. 16...Common bus, 17...Extended common bus. 21... Upper limit address register. 22...Lower limit address register. 23... Upper limit address comparator, 24... Lower limit address comparator. 25...or gate. 31...Amplifier. 32.33...and gate. 149

Claims (1)

[Claims] In a bidirectional bus expansion method that connects a microprocessor and a peripheral device via a bus amplifier, an upper limit address register sets the upper limit value of the address space of the expanded peripheral device, and a lower limit address sets the lower limit value of the address space. a register, an upper limit address comparator that compares an address signal specifying the peripheral device from the microprocessor with an address set in the upper limit address register, and an address signal specifying the peripheral device from the microprocessor and the lower limit address. Equipped with a lower limit address comparator that compares the address set in the register, the upper 111t address register and the lower limit address register are set according to a command from the microprocessor, and the address of the peripheral device specified by the microprocessor is set. When the upper limit value set in the upper limit address register is between the lower limit value set in the lower limit address register, the bus amplifier connected to the extension point is enabled and data is transmitted and received. Bus expansion method.