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EP0321156A3 - Data transfer controller - Google Patents

Data transfer controller Download PDF

Info

Publication number
EP0321156A3
EP0321156A3 EP19880311680 EP88311680A EP0321156A3 EP 0321156 A3 EP0321156 A3 EP 0321156A3 EP 19880311680 EP19880311680 EP 19880311680 EP 88311680 A EP88311680 A EP 88311680A EP 0321156 A3 EP0321156 A3 EP 0321156A3
Authority
EP
European Patent Office
Prior art keywords
bus
devices
performance
attached
ports
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19880311680
Other languages
German (de)
French (fr)
Other versions
EP0321156A2 (en
EP0321156B1 (en
Inventor
William M. Johnson
Timothy Alan Olson
Drew Jon Dutton
Sherman Lee
David William Stoenner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22452455&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=EP0321156(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP0321156A2 publication Critical patent/EP0321156A2/en
Publication of EP0321156A3 publication Critical patent/EP0321156A3/en
Application granted granted Critical
Publication of EP0321156B1 publication Critical patent/EP0321156B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the aforesaid transfer function in a manner that facilitates communication between the first and second set of devices from the compartive­ ly lower performance of the second set of devices. According to the preferred embodiment of the invention, a data transfer controller i.e., ("DTC") is disclosed that includes a set of direct memory access ("DMA") channels and an input/output controller comprising a set of address mapped I/O ports. Both the DMA channels and I/O ports may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (herein­ after referred to as a "Remote Bus"). The resulting DTC interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance.
EP88311680A 1987-12-15 1988-12-09 Data transfer controller between two busses Expired - Lifetime EP0321156B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/132,096 US5142672A (en) 1987-12-15 1987-12-15 Data transfer controller incorporating direct memory access channels and address mapped input/output windows
US132296 1993-10-05

Publications (3)

Publication Number Publication Date
EP0321156A2 EP0321156A2 (en) 1989-06-21
EP0321156A3 true EP0321156A3 (en) 1991-04-03
EP0321156B1 EP0321156B1 (en) 1998-03-04

Family

ID=22452455

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88311680A Expired - Lifetime EP0321156B1 (en) 1987-12-15 1988-12-09 Data transfer controller between two busses

Country Status (3)

Country Link
US (1) US5142672A (en)
EP (1) EP0321156B1 (en)
JP (1) JPH01205366A (en)

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5317715A (en) * 1987-12-15 1994-05-31 Advanced Micro Devices, Inc. Reduced instruction set computer system including apparatus and method for coupling a high performance RISC interface to a peripheral bus having different performance characteristics
US5546553A (en) * 1990-09-24 1996-08-13 Texas Instruments Incorporated Multifunctional access devices, systems and methods
US5333294A (en) * 1990-10-09 1994-07-26 Compaq Computer Corporation Configurable data width direct memory access device with a read address counter and a write address counter which increments the addresses based on the desired data transfer width
US5274763A (en) * 1990-12-28 1993-12-28 Apple Computer, Inc. Data path apparatus for IO adapter
US5369748A (en) * 1991-08-23 1994-11-29 Nexgen Microsystems Bus arbitration in a dual-bus architecture where one bus has relatively high latency
JPH0561951A (en) * 1991-08-30 1993-03-12 Fujitsu Ltd Image processor
CA2069711C (en) * 1991-09-18 1999-11-30 Donald Edward Carmon Multi-media signal processor computer system
US5341508A (en) * 1991-10-04 1994-08-23 Bull Hn Information Systems Inc. Processing unit having multiple synchronous bus for sharing access and regulating system bus access to synchronous bus
US5341495A (en) * 1991-10-04 1994-08-23 Bull Hn Information Systems, Inc. Bus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocols
JPH07122865B2 (en) * 1992-01-02 1995-12-25 インターナショナル・ビジネス・マシーンズ・コーポレイション Computer system having bus interface adapted to control operating speed of bus operation
WO1993023812A1 (en) * 1992-05-15 1993-11-25 Zenith Data Systems Corporation Enhanced parallel port
JPH05324546A (en) * 1992-05-18 1993-12-07 Canon Inc Information processing system
US5499384A (en) * 1992-12-31 1996-03-12 Seiko Epson Corporation Input output control unit having dedicated paths for controlling the input and output of data between host processor and external device
US5546548A (en) * 1993-03-31 1996-08-13 Intel Corporation Arbiter and arbitration process for a dynamic and flexible prioritization
US5550989A (en) * 1993-05-28 1996-08-27 International Business Machines Corporation Bridge circuit that can eliminate invalid data during information transfer between buses of different bitwidths
EP0706687A4 (en) * 1993-07-02 1997-07-16 Elonex Technologies Inc High-speed cpu interconnect bus architecture
JP3619532B2 (en) * 1993-11-08 2005-02-09 株式会社ルネサステクノロジ Semiconductor integrated circuit device
US5805927A (en) * 1994-01-28 1998-09-08 Apple Computer, Inc. Direct memory access channel architecture and method for reception of network information
US5828856A (en) * 1994-01-28 1998-10-27 Apple Computer, Inc. Dual bus concurrent multi-channel direct memory access controller and method
US5655151A (en) * 1994-01-28 1997-08-05 Apple Computer, Inc. DMA controller having a plurality of DMA channels each having multiple register sets storing different information controlling respective data transfer
DE4407571A1 (en) * 1994-03-07 1995-09-14 Siemens Ag Data processing system with buffer stores for synchronisation
US5572687A (en) * 1994-04-22 1996-11-05 The University Of British Columbia Method and apparatus for priority arbitration among devices in a computer system
US5526496A (en) * 1994-04-22 1996-06-11 The University Of British Columbia Method and apparatus for priority arbitration among devices in a computer system
US5649127A (en) * 1994-05-04 1997-07-15 Samsung Semiconductor, Inc. Method and apparatus for packing digital data
US5524216A (en) * 1994-05-13 1996-06-04 Hewlett-Packard Company Coherent transaction ordering in multi-tiered bus system
US5721882A (en) * 1994-08-05 1998-02-24 Intel Corporation Method and apparatus for interfacing memory devices operating at different speeds to a computer system bus
US5623694A (en) * 1994-10-03 1997-04-22 International Business Machines Corporation Aborting an I/O operation started before all system data is received by the I/O controller after detecting a remote retry operation
US5495614A (en) * 1994-12-14 1996-02-27 International Business Machines Corporation Interface control process between using programs and shared hardware facilities
US5619497A (en) * 1994-12-22 1997-04-08 Emc Corporation Method and apparatus for reordering frames
US5799207A (en) * 1995-03-28 1998-08-25 Industrial Technology Research Institute Non-blocking peripheral access architecture having a register configure to indicate a path selection for data transfer between a master, memory, and an I/O device
US5909560A (en) * 1995-06-06 1999-06-01 National Semiconductor Corporation Target peripheral device detection in a multi-bus system
US5673400A (en) * 1995-06-06 1997-09-30 National Semiconductor Corporation Method and apparatus for identifying and controlling a target peripheral device in a multiple bus system
WO1997044739A1 (en) * 1996-05-23 1997-11-27 Advanced Micro Devices, Inc. Apparatus for converting data between different endian formats and system and method employing same
EP0817085A1 (en) * 1996-06-25 1998-01-07 Motorola, Inc. Addressing means and method
US5715197A (en) 1996-07-29 1998-02-03 Xilinx, Inc. Multiport RAM with programmable data port configuration
US5832205A (en) * 1996-08-20 1998-11-03 Transmeta Corporation Memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed
US6199152B1 (en) 1996-08-22 2001-03-06 Transmeta Corporation Translated memory protection apparatus for an advanced microprocessor
US6504854B1 (en) 1998-04-10 2003-01-07 International Business Machines Corporation Multiple frequency communications
JP2000020490A (en) * 1998-07-01 2000-01-21 Fujitsu Ltd Computer having remote procedure calling mechanism or object request broker mechanism, data transfer method and transfer method storage medium
US6968469B1 (en) 2000-06-16 2005-11-22 Transmeta Corporation System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored
US7519779B2 (en) * 2002-08-26 2009-04-14 International Business Machines Corporation Dumping using limited system address space
US20050216716A1 (en) * 2004-03-29 2005-09-29 Hoffman Philip M System and method for licensing and distribution of I/O in partitioned computer systems
US20060069818A1 (en) * 2004-09-27 2006-03-30 Cliff Mather Synchronizing direct memory access and evacuation operations in a computer system
US10403333B2 (en) * 2016-07-15 2019-09-03 Advanced Micro Devices, Inc. Memory controller with flexible address decoding
WO2018145201A1 (en) 2017-02-08 2018-08-16 Upstream Data Inc. Blockchain mine at oil or gas facility
CA3088184A1 (en) 2018-01-11 2019-07-18 Lancium Llc Method and system for dynamic power delivery to a flexible datacenter using unutilized energy sources
US11016553B2 (en) 2018-09-14 2021-05-25 Lancium Llc Methods and systems for distributed power control of flexible datacenters
US10873211B2 (en) 2018-09-14 2020-12-22 Lancium Llc Systems and methods for dynamic power routing with behind-the-meter energy storage
US11031787B2 (en) 2018-09-14 2021-06-08 Lancium Llc System of critical datacenters and behind-the-meter flexible datacenters
US10367353B1 (en) 2018-10-30 2019-07-30 Lancium Llc Managing queue distribution between critical datacenter and flexible datacenter
US10452127B1 (en) * 2019-01-11 2019-10-22 Lancium Llc Redundant flexible datacenter workload scheduling
US11128165B2 (en) 2019-02-25 2021-09-21 Lancium Llc Behind-the-meter charging station with availability notification
WO2020227811A1 (en) 2019-05-15 2020-11-19 Upstream Data Inc. Portable blockchain mining system and methods of use
US11868106B2 (en) 2019-08-01 2024-01-09 Lancium Llc Granular power ramping
US11397999B2 (en) 2019-08-01 2022-07-26 Lancium Llc Modifying computing system operations based on cost and power conditions
US11016458B2 (en) 2019-10-28 2021-05-25 Lancium Llc Methods and systems for adjusting power consumption based on dynamic power option agreement
US11042948B1 (en) 2020-02-27 2021-06-22 Lancium Llc Computing component arrangement based on ramping capabilities
US12099873B2 (en) 2020-08-14 2024-09-24 Lancium Llc Power aware scheduling

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0079140A1 (en) * 1981-10-15 1983-05-18 Convergent Technologies Inc. Multiple computing systems and communication bus structure therefor
US4568930A (en) * 1983-01-21 1986-02-04 E-Systems, Inc. Multinodal data communication network
EP0204960A2 (en) * 1985-06-14 1986-12-17 International Business Machines Corporation Multiple port integrated DMA and interrupt controller and arbitrator

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3940743A (en) * 1973-11-05 1976-02-24 Digital Equipment Corporation Interconnecting unit for independently operable data processing systems
US4313160A (en) * 1976-08-17 1982-01-26 Computer Automation, Inc. Distributed input/output controller system
US4309754A (en) * 1979-07-30 1982-01-05 International Business Machines Corp. Data interface mechanism for interfacing bit-parallel data buses of different bit width
IT1121031B (en) * 1979-09-19 1986-03-26 Olivetti & Co Spa MULTIPROCESSOR DATA PROCESSING SYSTEM
JPS58223833A (en) * 1982-06-23 1983-12-26 Fujitsu Ltd Direct memory access control system
JPS59721A (en) * 1982-06-28 1984-01-05 Panafacom Ltd Control system of information transfer
JPS6010379A (en) * 1983-06-30 1985-01-19 Nec Corp Data transfer system of data processing system
JPS61285566A (en) * 1985-06-13 1986-12-16 Panafacom Ltd Input and output controller
JPS6275867A (en) * 1985-09-30 1987-04-07 Toshiba Corp Control system for data transfer
US4847750A (en) * 1986-02-13 1989-07-11 Intelligent Instrumentation, Inc. Peripheral DMA controller for data acquisition system
US4821185A (en) * 1986-05-19 1989-04-11 American Telephone And Telegraph Company I/O interface system using plural buffers sized smaller than non-overlapping contiguous computer memory portions dedicated to each buffer
US4851990A (en) * 1987-02-09 1989-07-25 Advanced Micro Devices, Inc. High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure
US4947366A (en) * 1987-10-02 1990-08-07 Advanced Micro Devices, Inc. Input/output controller incorporating address mapped input/output windows and read ahead/write behind capabilities

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0079140A1 (en) * 1981-10-15 1983-05-18 Convergent Technologies Inc. Multiple computing systems and communication bus structure therefor
US4568930A (en) * 1983-01-21 1986-02-04 E-Systems, Inc. Multinodal data communication network
EP0204960A2 (en) * 1985-06-14 1986-12-17 International Business Machines Corporation Multiple port integrated DMA and interrupt controller and arbitrator

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
COMPUTER DESIGN, vol. 21, no. 2, February 1982, pages 121-126, Winchester, MA, US; R. GARROW: "Dual-bus design for a microcomputer" *
ELECTRICAL DESIGN NEWS, vol. 27, no. 5, March 1982, pages 117-125, Boston, US; D.L. RUHBERG et al.: "Eliminate system growth pains with a muP/controller interface" *
NACHRICHTENTECHNIK-ELEKTRONIK, vol. 29, no. 6, 1979, pages 229-232; W. CIMANDER et al.: "Mehrmikrorechnersysteme mit Registerkopplung" *

Also Published As

Publication number Publication date
EP0321156A2 (en) 1989-06-21
US5142672A (en) 1992-08-25
EP0321156B1 (en) 1998-03-04
JPH01205366A (en) 1989-08-17

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