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JPS59200437A - Cutting method - Google Patents

Cutting method

Info

Publication number
JPS59200437A
JPS59200437A JP58072932A JP7293283A JPS59200437A JP S59200437 A JPS59200437 A JP S59200437A JP 58072932 A JP58072932 A JP 58072932A JP 7293283 A JP7293283 A JP 7293283A JP S59200437 A JPS59200437 A JP S59200437A
Authority
JP
Japan
Prior art keywords
groove
wafer
cutter
cutting
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58072932A
Other languages
Japanese (ja)
Inventor
Ichiro Kato
一郎 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58072932A priority Critical patent/JPS59200437A/en
Publication of JPS59200437A publication Critical patent/JPS59200437A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To cut a wafer for a semiconductor laser along a cleavage plane even when there is a difference between angles within a predetermined range between the direction of a groove through selective etching and the direction of cleavage in the wafer by bringing cutter into contact with the dovetail groove, relatively moving the cutter and cutting the wafer. CONSTITUTION:A surface to which the side end sections of dovetail grooves 4... are opened forms a cleavage plane. The direction orthogonal to the dovetail grooves 4... is directed in the direction of 110 as the direction of a line crossing of a main surface 001 and the cleavage plane, and a V-shaped groove 5 is formed through selective etching in the direction. A surface to which the side end section of the V-shaped groove 5 is opened is represented as a 110 surface, and forms a surface parallel with the resonant end surface of a semiconductor laser. A wafer 2 to which the dovetail grooves 4... are shaped is fixed onto a table, a cutter 6 is brought into contact with one end section of the bottom 3 of the dovetail groove 4 at the central section of the wafer 2 or a section entering to the inside from an end section, and said section is slotted and cloven slightly. When the cutter 6 is further slotted and the table is moved under the state in which the cutter is tilted at a fixed angle theta, the edge 7 is shifted relatively along a cleavage prearranged line on the bottom 3, and the wafer 2 is cut into two sections.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体レーザ用のウェハを割断して共振端面
を有する短冊状体を得るための割断方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a cutting method for cutting a wafer for a semiconductor laser to obtain a strip-shaped body having a resonant end face.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

近時、半導体レーザがたとえば光方式のゲイジタル・オ
ーディオ・ディスクなどの分野に普及。
Recently, semiconductor lasers have become popular in fields such as optical gain digital audio discs.

浸透Ifしている。この半導体製造は、次のような工程
で行われている。すなわち、ひ化ガリウム(GaAs 
)ウェハに溝9段差等をエツチングで形成したのち、多
層膜(Qa Ae As層)をエピタキシャル成長させ
る。ついで、電極金属としてのAuを形成したのち、共
振端面を作るための割断作業を襞間を利用して行う。そ
して、との襞間後の細長い短冊状のままで共振端面に保
護膜を付ける。つぎに、チップに切断後、このチップを
Cu、Si 等のサブマウント基板にろう材を介してマ
ウントしてノくツケージに実装1組立てを行っている。
Penetration If. This semiconductor manufacturing is performed through the following steps. That is, gallium arsenide (GaAs
) After forming 9 grooves on the wafer by etching, a multilayer film (Qa Ae As layer) is epitaxially grown. Next, after forming Au as an electrode metal, a cutting operation for creating a resonant end face is performed using the gaps between the folds. Then, a protective film is attached to the resonant end face while remaining in the shape of an elongated strip between the folds. Next, after cutting into chips, the chips are mounted on a submount substrate made of Cu, Si, etc. via a brazing material, and assembled into a socket cage.

ところで、上記GaAsウェハの割断作業においては、
共振器長が一定になるようにしなければならない。しか
し、一般にGaAsウエノ・は極めて薄く取扱中に破損
しやすい。そのうえ割断中に筋模様が生じ易く、筋模様
(損傷)が生じた場合には、後になって性能低下する傾
向があるので、歩留がすこぶる悪かった。
By the way, in the above-mentioned cutting operation of the GaAs wafer,
The resonator length must be kept constant. However, GaAs wafers are generally extremely thin and easily damaged during handling. In addition, streaks tend to occur during cutting, and if streaks (damage) occur, the performance tends to deteriorate later, resulting in a very low yield.

そこで、従来第1図に示すように、マスクツくター成し
、この7字溝(1)に沿って例えば機械的割断を行って
いた。しかるに、骨間方向とマスクツくターンを用いて
形成された7字溝の伸長方向との平行度を10秒以下に
することは困難である。そのため襞間面である割断面の
き装線が常に7字溝の谷底である最下部をなす線状部分
に沿って伝播することは通常なく、7字溝のいずれか一
方の斜面を上る傾向が生じる。その結果、割断面両側の
結晶体の剛性に不均衡が生じ、割断面は剛性が弱い方へ
曲ってしまい、微小階段(数〜数百穴の段差で、ジ盲グ
(Joy)とも呼ばれる。)が発生することによシ共振
性゛能劣化の一つの原因となっている。しかも、割断の
ための刃物が当接した部位で必ずしも微小襞間が発生す
るとは限らず、ずれだ部位で発生するとやはり剛性の不
均衡が生じ、割断面が曲ってしまう欠点を有している。
Therefore, conventionally, as shown in FIG. 1, a mask cutter was formed and, for example, mechanical cutting was performed along the 7-shaped groove (1). However, it is difficult to make the parallelism between the interosseous direction and the extending direction of the 7-shaped groove formed using the mask turn less than 10 seconds. Therefore, the crease line on the fractured surface, which is the inter-fold surface, does not always propagate along the bottom linear part of the figure-7 groove, but tends to go up one slope of the figure-7 groove. occurs. As a result, an imbalance occurs in the rigidity of the crystals on both sides of the fractured surface, and the fractured surface bends toward the side with weaker rigidity, resulting in micro-stairs (steps with several to hundreds of holes, also called joy). ) is one of the causes of deterioration of resonance performance. Moreover, minute creases do not necessarily occur at the part where the cutter makes contact, and if they occur at a misaligned part, there is still an imbalance in rigidity, which has the disadvantage of bending the cut surface. .

〔発明の目的〕[Purpose of the invention]

本発明は、上記事情を参酌してなされたもので、半導体
レーザ用のウェハに選択エツチングによる溝方向と骨間
方向との間に一定の範囲内で角度差があっても、割断を
譬開面に沿って行うことのできる割断方法を提供するこ
とを目的とする。
The present invention has been made in consideration of the above circumstances, and even if there is an angular difference within a certain range between the direction of grooves formed by selective etching on a wafer for semiconductor lasers and the direction between the bones, it is possible to prevent cutting. The purpose of the present invention is to provide a cutting method that can be performed along a surface.

〔発明の概要〕[Summary of the invention]

単結晶ウェハの襞間を生じさせる割断予定線に沿ってあ
らかじめマスクパターン等を用いて選択エツチングを行
うことにより所望間隔の平行なあシ溝を形成し、上記あ
シ溝に刃物を当接させたのち、刃物を相対的に移動させ
ることによシ割断を行うものである。
Selective etching is performed in advance using a mask pattern or the like along the planned cutting line that creates the creases in the single crystal wafer, thereby forming parallel grooves at desired intervals, and a cutter is brought into contact with the grooves. Afterwards, cutting is performed by relatively moving the blades.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を図面を参照して詳述する。ま
ず、第2図に示す厚さがほぼ100μm、 −辺が20
〜25朋の正方形状の単結晶GaAsウェハ(2)のレ
ーザ発振部に遠い方の主面(001) (裏面に相当)
に対して、例えば33%Cry3− HF系のエツチン
グ液でエツチングを行い、顕微鏡によりビットを観察す
ることによJ (110)方向をさがす。この(110
)方向は主面(001)と襞間面(110)との交線方
向である。しかして、等間隔で平行なスリットが形成さ
れているマスクパターン(図示せず)をスリットの長手
方向が(110)方向と平行になるようにウェハ(2)
の主面(ooi)に当接し、第3図に示す平坦な底面(
3)を有するあシ溝(4)・・・を、第4図に示すよう
に、等間隔で多数本選択エツチングによシ形成する。こ
れらsb溝(4)・・・の深さDは、ウェハ(2)の厚
さの10〜30%となる10〜30μmとなるようにエ
ツチングする。この深さDが、これよりも深ければ破断
しやすくなって取扱いが困難となるため好ましくなく、
逆に浅ければ後述する効果を十分に発揮することができ
ない。このとき使用するエツチング液としてはBr、 
−CH,OH系のものが最適であって、たとえば13r
、濃度1重量%のものを用いた場合、エツチング時間は
1〜3分が好ましい。そして、第3図に示すように、あ
り溝(4)・・・の側端部が開口している面は襞間面(
110)となっている。また、あシ溝(4)・・・に直
交する方向は、主面(ooi)と襞間面(110)との
交線方向である[:110)方向となっていて、この方
向に選択エツチングすると、第1図にも示した7字溝(
5)が形成される。この7字溝(5)の側端部が開口し
ている面は(110)面であって、本実施例の割断方法
により得ようとする半導体レーザの共振端面と平行な面
となっている。ついで、あシ溝(4)・・・が形成され
たウエノ・(2)をテーブル(図示せず)上に固定する
。このときテーブルの移動方向とあシ溝(4)・・・と
が一致するように設置する。さらに、第5図に示す刃物
(6)をウニ・・(2)中央部にあるあシ溝(4)の底
面(3)の一端部又は端部から311!以下の距離で内
側に入った所にあて、3〜10μm切込み微小襞間させ
る。上記刃物(6)は、第6図に示すように、直線状の
刃部(力を有し、その屹水角βは2〜10度が好適であ
る。さらに、刃物(6)を5〜10μm切込ませ、刃物
(6)を一定角度θ傾斜させた状態でテーブルを動かす
。すると、刃部(7)は底面(3)にある伸開予定線に
沿って相対的に移動し、ウェハ(2)は二つの部分に割
断される。しかして、同様の割断操作を繰返し半分、半
分と工程し、最終的に幅0.25 mynの短冊状体を
作製する。このように本実施例の割断方法は、あり溝(
4)・・・に沿りて臂開を行わせるようにしているので
、選択エツチングによる。l溝(4)・・・の伸長方向
と襞間方向との間に角度差が存在していてもあシ溝(4
)・・・の各底面(3)・・・内KW開予定扉が存在す
る限り(あり溝(4)・・・の伸長方向と伸開方向との
角度差は、±3分程度まで許容される。)、割断き裂が
あり溝(4)・・・の斜面を上るようなことはない。し
たがって、割断された左右両側結晶体間に剛性の不均衡
が発生することはない。したがって、割断面が剛性が弱
い方向へ曲ってしまうことにより、損傷が生じることを
防止して、欠陥のない美麗な襞間面(共振端面)を得る
ことかできる。しかも、溝幅を広く取れるので、刃物(
5)の切込みが容易となる。したがって、割断に1字溝
を利用する場合に比べ共振端面の品質が向上し、歩留が
向上する。
Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. First, the thickness shown in Figure 2 is approximately 100 μm, and the -side is 20 μm.
The main surface (001) of the ~25 mm square single-crystal GaAs wafer (2) that is far from the laser oscillation part (corresponds to the back surface)
For example, the J (110) direction is searched by etching with a 33% Cry3-HF based etching solution and observing the bit with a microscope. This (110
) direction is the direction of the intersection between the main surface (001) and the interfold surface (110). A mask pattern (not shown) in which parallel slits are formed at equal intervals is placed on the wafer (2) so that the longitudinal direction of the slits is parallel to the (110) direction.
The flat bottom surface (ooi) shown in FIG.
3) are formed by selective etching in large numbers at equal intervals, as shown in FIG. The depth D of these sb grooves (4) is etched to 10 to 30 μm, which is 10 to 30% of the thickness of the wafer (2). If this depth D is deeper than this, it is not preferable because it becomes easy to break and becomes difficult to handle.
On the other hand, if it is shallow, the effects described below cannot be fully exhibited. The etching solution used at this time is Br,
-CH,OH type is most suitable, for example 13r
, when a concentration of 1% by weight is used, the etching time is preferably 1 to 3 minutes. As shown in Fig. 3, the surface where the side ends of the dovetail grooves (4) are open is the inter-fold surface (
110). In addition, the direction perpendicular to the foot grooves (4) is the [:110) direction, which is the direction of intersection between the main surface (ooi) and the inter-fold surface (110), and the selection is made in this direction. When etched, the figure 7 groove (
5) is formed. The surface on which the side end of this 7-shaped groove (5) is open is the (110) plane, which is parallel to the resonant end surface of the semiconductor laser to be obtained by the cutting method of this example. . Next, the wafer (2) in which the foot grooves (4) have been formed is fixed on a table (not shown). At this time, the table is installed so that the moving direction of the table matches the foot grooves (4). Furthermore, the cutlery (6) shown in FIG. Place it on the inside at the following distance and make a 3 to 10 μm incision to create minute folds. As shown in FIG. A 10 μm cut is made and the table is moved with the blade (6) tilted at a constant angle θ.Then, the blade (7) moves relatively along the planned expansion line on the bottom surface (3) and cuts the wafer. (2) is cut into two parts.The same cutting operation is then repeated in half and half to finally produce a strip-shaped body with a width of 0.25 myn.In this way, this example The cutting method is dovetail groove (
4) The arms are opened along the lines, so selective etching is used. Even if there is an angular difference between the elongation direction of the l groove (4) and the direction between the folds, the leg groove (4)...
)... each bottom (3)... As long as the inner KW opening door is present (the angular difference between the extension direction and the extension/opening direction of the dovetail groove (4)... is allowed up to about ±3 minutes. ), there is a splitting crack and it does not climb up the slope of groove (4)... Therefore, an imbalance in rigidity does not occur between the cut right and left crystal bodies. Therefore, it is possible to prevent damage caused by bending the fractured surface in a direction where the rigidity is weak, and to obtain a beautiful interfold surface (resonant end surface) without defects. Moreover, since the groove width can be widened, the blade (
5) The cutting becomes easier. Therefore, the quality of the resonant end face is improved compared to the case where a single-shaped groove is used for cutting, and the yield is improved.

なお、上記実施例においては、割断は直線状の刃部を有
する刃物によシ行っているが、屹水角βが3〜4度の自
由回転ソロパン玉状の刃物を用いて割断してもよい。さ
らに、上記実施例における割断対象はGaAsであるが
、選択エツチングによシ形成したアリ溝を利用して割断
するのであれば、Gap、 InSb、 Zn8等にも
本発明を適用することができる。さらにまた、選択エツ
チング液を使用しなくとも、例えば反応性イオンエツチ
ング(React 1veIon Etching )
などの方法で襞間面とウエノ・主面との交線方向に溝底
が比較的平坦な溝を形成して、割断してもよい。さらに
、平坦な底面を有する溝は、ウェハ(2)の端部にのみ
形成して割断してもよい。
In the above embodiments, the cutting was performed using a knife with a straight blade, but it is also possible to cut using a free-rotating Solopan ball-shaped knife with a cutting angle β of 3 to 4 degrees. good. Further, although the material to be cut in the above embodiment is GaAs, the present invention can also be applied to Gap, InSb, Zn8, etc. if the material is cut using the dovetail groove formed by selective etching. Furthermore, even without using a selective etching solution, for example, reactive ion etching (React Ion Etching) can be used.
A groove with a relatively flat groove bottom may be formed in the direction of the intersection between the inter-fold surface and the main surface of the wafer, and then cut. Furthermore, the groove with a flat bottom surface may be formed only at the end of the wafer (2) and then cut.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、割断方向に沿って選択エツチングによ
シアり溝を形成し、このあり溝を利用して割断を行うよ
うにしているので、あシ溝の伸長方向と襞間方向との間
に角度差が存在していても、あシ溝の底面内に襞間面が
存在する限シ、割断面つ荻9 の跡ス紘き製線が溝の斜面を上るようカことはない。し
たがって、欠陥のない美麗な勢開面を得ることができる
。しかも、溝幅を広くとれるので、刃物の切込みが容易
となる。ことに、本発明を半導体レーザ用チップの作製
に適用した場合、割断にV字溝を利用するのに比べ、品
質及び歩留を向上させることができる。
According to the present invention, the shear grooves are formed by selective etching along the cutting direction, and the dovetail grooves are used to perform cutting, so that the extension direction of the leg grooves and the direction between the folds are different. Even if there is an angular difference between the grooves, as long as there is an inter-fold surface within the bottom of the groove, the grooved wire will not climb up the slope of the groove. . Therefore, it is possible to obtain a beautiful, defect-free surface. Moreover, since the groove width can be made wider, cutting with a blade becomes easier. In particular, when the present invention is applied to the production of semiconductor laser chips, quality and yield can be improved compared to using V-shaped grooves for cutting.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のGaAsウニ7%の割断に利用されてい
るV字溝を示す断面図、第2図は本発明の一実施例にお
けるあシ溝形成方向を示す斜視図、第3図はあシ溝及び
V字溝の配向関係を示す要部拡大斜視図、第4図は選択
エツチングにより形成された複数のあシ溝を示す斜視図
、第5図及び第6図は刃物による割断を示す説明図であ
る。 (2):ウェハ、      (3) :あり溝。 +5) : V字溝、     (61:刃 物。 代理人 弁理士  則 近 憲 佑 (ほか1名)
FIG. 1 is a sectional view showing a V-shaped groove used in the conventional cutting of 7% GaAs sea urchin, FIG. 2 is a perspective view showing the direction in which the groove is formed in an embodiment of the present invention, and FIG. FIG. 4 is a perspective view showing a plurality of grooves formed by selective etching, and FIGS. FIG. (2): Wafer, (3): Dovetail groove. +5): V-shaped groove, (61: Knives. Agent: Patent attorney Noriyuki Chika (and 1 other person)

Claims (6)

【特許請求の範囲】[Claims] (1)単結晶ウェハの襞間を生じさせる割断予定線に沿
って選択エツチングを行い底面がほぼ平坦な溝を形成さ
せる方法と、上記溝の底面に刃物を当接させたのちこの
刃物を上記単結晶ウニノーに対して相対的に移動させ上
記単結晶ウェハを割断する方法とを具備することを特徴
とする割断方法。
(1) A method of selectively etching a single-crystal wafer along a planned cutting line that creates creases to form a groove with a substantially flat bottom, and a method of abutting a cutter against the bottom of the groove and then moving the cutter as described above. A cutting method characterized by comprising: a method of cutting the single crystal wafer by moving the single crystal wafer relative to the single crystal wafer.
(2)溝はあシ溝であることを特徴とする特許請求の範
囲第1項記載の割断方、法。
(2) The cutting method according to claim 1, wherein the groove is a reed groove.
(3)単結晶ウェハはひ化ガリウムであることを特徴と
する特許請求の範囲第1項又は第2項記載の割断方法。
(3) The cutting method according to claim 1 or 2, wherein the single crystal wafer is gallium arsenide.
(4)溝の深さは単結晶ウエノ・の厚さの10〜30%
であることを特徴とする特許請求の範囲第1項又は第2
項記載の割断方法。
(4) The depth of the groove is 10 to 30% of the thickness of the single crystal Ueno.
Claim 1 or 2 characterized in that
Cutting method described in section.
(5)溝の伸長方向と上記溝の底面における骨間方向と
の角度差は3分以下であることを特徴とする特許請求の
範囲第1項又は第2項記載の割断方法。
(5) The cleaving method according to claim 1 or 2, wherein the angular difference between the extending direction of the groove and the interosseous direction at the bottom of the groove is 3 minutes or less.
(6)選択エツチングはBr、 −CHsOH系のエツ
チング液で行うことを特徴とする特許請求の範囲第1項
、xisii項記載の割断方法。
(6) The cutting method as set forth in claims 1 and xisii, wherein the selective etching is performed with a Br, -CHsOH based etching solution.
JP58072932A 1983-04-27 1983-04-27 Cutting method Pending JPS59200437A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58072932A JPS59200437A (en) 1983-04-27 1983-04-27 Cutting method

Applications Claiming Priority (1)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4927778A (en) * 1988-08-05 1990-05-22 Eastman Kodak Company Method of improving yield of LED arrays
US5593815A (en) * 1989-07-31 1997-01-14 Goldstar Co., Ltd. Cleaving process in manufacturing a semiconductor laser
JP2011005741A (en) * 2009-06-25 2011-01-13 Mitsuboshi Diamond Industrial Co Ltd Method of dividing brittle material substrate
WO2022057735A1 (en) * 2020-09-17 2022-03-24 深圳市中光工业技术研究院 Method for increasing precision of flat edge of semiconductor wafer, and laser chip

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4927778A (en) * 1988-08-05 1990-05-22 Eastman Kodak Company Method of improving yield of LED arrays
US5593815A (en) * 1989-07-31 1997-01-14 Goldstar Co., Ltd. Cleaving process in manufacturing a semiconductor laser
JP2011005741A (en) * 2009-06-25 2011-01-13 Mitsuboshi Diamond Industrial Co Ltd Method of dividing brittle material substrate
WO2022057735A1 (en) * 2020-09-17 2022-03-24 深圳市中光工业技术研究院 Method for increasing precision of flat edge of semiconductor wafer, and laser chip

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