JPS59156016A - Cmos amplifier circuit - Google Patents

Abstract

PURPOSE:To obtain a CMOS amplifier circuit with high accuracy without any offset voltage by connecting a capacitor to an input side so as to store the offset voltage of the amplifier circuit at the input side and amplifying a signal in the form that the offset voltage of the amplifier is cancelled. CONSTITUTION:When the amplifier circuit is in inoperating state, a switch 32 is turned off, switches 33, 34, 35 are turned on, and when the amplifier circuit is in operating state, the switch 32 is turned on and the switches 33, 34, 35 are turned off. A potential of a node 7 in the inoperating state is an equipotential to that of an input terminal 4 applied with a reference voltage, the offset voltage appearing at nodes 121, 122 appears at nodes 37, 36 and is stored in capacitors 30, 31. An input signal applied to an input terminal 3 in the operating state is applied to a transistor 15 after the offset voltage stored in the capacitor 30 is subtracted from the input signal, and a reference applied to the input terminal 4 is applied to a transistor 17 after the offset voltage stored in the capacitor 31 is subtracted from the reference voltage, thereby causing an output voltage without any offset voltage at output terminals 5, 6.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CMO8 amplifier circuit which has a capacitor for compensating offset voltage and a switch for clock operation and is used as the first stage button of a high precision comparator circuit.

Conventionally, when configuring a comparator circuit using this type of amplifier circuit, the circuit state of the comparator circuit is divided into an operating state and a non-operating state by a clock signal, and the offset voltage of the first stage differential amplifier is set in the non-operating state. The offset voltage is calculated by subtracting the offset voltage stored in the capacitor from the signal voltage amplified by the differential amplifier when the circuit is in operation and outputting the result. The purpose is to perform high-precision comparisons with few errors. However, since this conventional differential comparator circuit detects the offset voltage of the first stage differential amplifier on the output side, it is good when the voltage gain of the differential amplifier is small or when the offset voltage seen from the input side is small. When the voltage gain is high and the offset voltage seen from the input side is relatively large, as in the case of a CMO8 differential amplifier, [input offset in voltage x voltage gain] exceeds the output dynamic range and the input offset voltage Since the offset voltage cannot be amplified sufficiently linearly, the offset voltage cannot be accurately stored in the capacitor connected to the output side, resulting in a decrease in accuracy.

The object of the present invention is to store the offset voltage of the amplifier circuit on the input side by connecting a capacitor to the input side, and to subtract the offset voltage from the input signal before inputting it to the amplifier circuit. By amplifying the signal in a form that eliminates the offset voltage of the amplifier circuit, regardless of the magnitude of the voltage gain or the magnitude of the offset voltage, a highly accurate CMO8 amplifier circuit with no offset voltage can be obtained. be.

The CMO8 amplifier circuit of the present invention includes a first 9MO8) transistor whose source electrode is connected to a first power supply terminal and whose gate electrode is connected to a drain electrode, and whose drain electrode is connected to the first pMOSMOS transistor in-electrode. a 10th HMOS') transistor whose source electrode is connected to the first power supply terminal and whose gate electrode is connected to the first power supply terminal;
A second pMO8MOS transistor drain electrode connected to the drain electrode of the
a second 1MO8) transistor whose drain electrode is connected to the drain electrode of the first nMOS transistor and whose source electrode is connected to the source electrode of the first nMOS transistor; a first capacitor whose one end is connected to the gate electrode of the transistor; a first switch connected between an input terminal of the first capacitor and the other end of the first capacitor and opened and closed by a first clock signal; a second input terminal and a gate electrode of the second nMOS transistor; a second switch connected between the second input terminal and the other end of the first capacitor and opened and closed by a second clock signal; a third switch connected between one end of the first capacitor and the drain electrode of the first pMOS transistor and opened and closed by the second clock signal; and a drain electrode of the second nMOS transistor. , a fourth switch connected between the gate electrode and opened/closed by the second clock signal, and a first switch connected to the drain/electrode of the first transistor.
and a second output terminal connected to the second pMOS transistor I/electrode.

Next, explanation will be given with reference to the drawings.

FIG. 1 shows a first-stage differential amplifier circuit of a CMO8 converter circuit having a conventional configuration. The basic configuration of this differential amplifier circuit is pMOS transistors 14 and 16 and nMO
8 MOS transistor 15.18 years old, n
The MOS transistor is connected to terminal 1 so that it functions as a constant current source.
An appropriate gate bias paper pressure is applied to 25.

In this circuit, an input signal is applied to an input terminal 3, and a reference voltage is applied to an input terminal 4. In the non-operating state, a negative voltage is applied to terminal 1 and a positive voltage is applied to terminal 2, so that 1MO8) transistors 12, 22.24 and 9MO8) transistors 13, 23.25 are in a conductive state. , nMO8) transistor 10 and pMO8) transistor 1 are in the cut-off state. Note that a positive power source is connected to the terminal 120, and an appropriate bias voltage is applied to the terminal 124. Therefore, output terminals 5 and 6 are terminals 124
The potential is the same as the bias voltage of On the one hand,
Since transistors 12 and 13 are conductive, n
The gate electrode of the MOS transistor 15 is at the same potential as the gate electrode of the nMOS transistor 17, and a reference voltage is applied thereto. Therefore, since the gate voltages of nMOS transistors 15 and 17 are at the same potential, terminal 121
An output offset voltage appears at and 122. This voltage is stored in capacitors 20 and 21 as a difference from the bias voltage applied to terminal 124.

When the circuit is in operation, a positive voltage is applied to terminal 1 and a negative voltage is applied to terminal 2, so transistor 10.11
becomes equal conduction state, and transistors 12, 13, 22, 2
3.24.25 will be cut off. Therefore, the input signal applied to terminal 3 is applied to the gate electrode of transistor 15, and the reference voltage of terminal 4 is applied to the gate electrode of transistor 17, so that the difference voltage between them is amplified and applied to terminals 121 and 122. appear. However, terminal 12
The voltage appearing at 1,122 K also includes an offset voltage. Their offset voltage is the capacitor 20.
Since the offset voltages are the same as those stored in 21, these offset voltages appear at the output terminal 5.6 with these offset voltages subtracted. Therefore, input terminals 3, 4 and output terminal 5
, 6, there appears to be no offset voltage, so it can be used as the first stage amplifier of a high precision comparator. However, since this type of CMO8 differential amplifier generally has an extremely high degree of amplification, if the difference between the gate threshold voltages of transistors 15 and 17 is large to some extent, the output voltage will be saturated, and the difference in gate threshold voltages, that is, the input offset. Since the voltage cannot be reflected in the optical output, the accuracy of the offset 'tE voltage stored in the capacitor 2.0.21 in the non-operating state decreases, and the disadvantage is that the offset voltage cannot be sufficiently reduced in the operating state. be.

FIG. 2 shows an embodiment of the present invention, showing a first-stage differential amplifier circuit of a CMOS comparator circuit.

The switches 32, 33, 34, and 35 have a pMO8 transistor and a MOS transistor connected in parallel.
．． 11, but is expressed as a switch for simplicity. When the circuit is inactive, switch 32 is off and switches 33, 34 and 35 are on; when the circuit is active, switch 32 is on and switch 3 is off.
3,34°35 is in the off state. When inactive,
Node 121 is at the same potential as node 37, and node 22 is at the same potential as node 3.
Since the potential of node 7 is the same as that of input terminal 4 to which the reference voltage is applied, node 121
The offset voltage appearing at node 122 is at node 37.3.
6, this offset voltage is applied to capacitor 3.
0.31.

When the circuit is in operation, the state of the switch is as shown in FIG. Marked 71+
11, and the reference voltage applied to the input terminal 4 is applied to the gate electrode of the transistor 17 after the offset voltage stored in the capacitor 31 has been subtracted. Output voltages with no offset voltage are applied to the output terminals 5 and 6, where 1<1.

In the circuit according to the present invention, the output voltage does not saturate due to the offset voltage when in the non-operating state, and the offset voltage is accurately stored in the capacitor, so the accurate comparison result is used as the output voltage when the circuit is in the operating state. It can be superior to the terminal IP width.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional CMO8 amplifier circuit, and FIG. 2 is a circuit diagram showing an embodiment of the CMO8 amplifier circuit according to the present invention. 32. 33, 34, 35 are switches, 15, 17° 18
is nMOS transfer, 1'4, 16u
pMOs transistor, 30.31 is the container, 3 is the No. 16 input terminal, 4 is the reference voltage input terminal, 5 and 6 are the output terminals. vJ1 diagram? 5 sake Z7

Claims (1)

[Claims] a first pMOS transistor whose source electrode is connected to a first power supply terminal and whose gate electrode is connected to a drain electrode; and a first nMOS transistor whose drain electrode is connected to the drain electrode of said first pMOS transistor) a second pMOS transistor whose source electrode is connected to the first power supply terminal and whose gate electrode is connected to the drain electrode of the first pMOS transistor; and a second pMOS transistor whose drain electrode is connected to the second pMOS transistor (8) a second nMOS transistor connected to the drain electrode of the transistor and having a source electrode connected to the source electrode of the first nMOS transistor; a second nMOS transistor having a drain electrode connected to the source electrode of the first nMOS transistor; a third n whose electrode is connected to the second power supply terminal and whose source electrode is grounded;
a MOS transistor; a first capacitor having one end connected to the gate electrode of the first nMOS transistor;
a first switch connected between a first input terminal and the other end of the first capacitor t and opened and closed by a first clock signal; a second input terminal and the second nMOS transistor; The capacitance of the second capacitor connected between the gate electrode and the second capacitor
a second switch connected between the input terminal of the first capacitor and the other end of the first capacitor and opened and closed by a second clock signal; and one end of the first capacitor and the first pMOSMOS transistor in-electrode. a third switch connected between them and opened and closed by the second clock signal; and a fourth switch connected between the drain electrode and gate electrode of the second nMOS transistor and opened and closed by the second clock signal. A CMOS amplifier comprising: a first output terminal connected to the drain electrode of the first pMOS transistor; and a second output terminal connected to the drain electrode of the second pMOS transistor. circuit.