JPS5910271A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5910271A JPS5910271A JP10938483A JP10938483A JPS5910271A JP S5910271 A JPS5910271 A JP S5910271A JP 10938483 A JP10938483 A JP 10938483A JP 10938483 A JP10938483 A JP 10938483A JP S5910271 A JPS5910271 A JP S5910271A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- high melting
- electrode
- point metal
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000002844 melting Methods 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- 230000008018 melting Effects 0.000 claims abstract description 39
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 abstract description 31
- 239000011229 interlayer Substances 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 230000001590 oxidative effect Effects 0.000 abstract description 4
- 238000007740 vapor deposition Methods 0.000 abstract description 2
- 238000004299 exfoliation Methods 0.000 abstract 1
- 239000011521 glass Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000002161 passivation Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 229910052750 molybdenum Inorganic materials 0.000 description 5
- 239000011733 molybdenum Substances 0.000 description 5
- 239000003870 refractory metal Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000003595 mist Substances 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000000859 sublimation Methods 0.000 description 2
- 230000008022 sublimation Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 150000003017 phosphorus Chemical class 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は高い温度に耐えることができる半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device that can withstand high temperatures.
高融点金属／多結晶ノリコン捷だは高融点金属シリサイ
ド／多結晶ソリコンの二重電極構造は既に知られている
。高融点金属／多結晶ンリコンから成る電極においては
、電極形成後の高温熱処理工程で高融点金属と多結晶ン
リコンが反応し、界面に高融点金属ソリサイド層が生じ
る。このノリサイド層の体積は反応前の高融点金属と７
リコノの体積の和よりも太きい。したがって、この現象
に起因して、高融点金属にわれが生じたり、電極がシリ
コン酸化膜下地等からはがれるという欠点があった。こ
のような現象は、高融点金属の電極を直接ンリコン基板
につけた場合にも同様に見られる。それ故、通常、基板
ンリコ／と高融点金属電極が接触する部分を有する半導
体装置では、その製造過程で経る熱処理温度を約５００
℃以下に限定され、高融点金属の長所である高耐熱性が
生かされてい々い。高融点金属シリサイド／多結晶７リ
コンから成る電極はこのような欠点を持っておらず、安
定である。しかしながら、高融点金属シリサイド膜は、
同じ高融点金属膜と較べて、抵抗率が約１桁以上高いと
いう欠点を持っている。Dual electrode structures of high melting point metal/polycrystalline silicon and high melting point metal silicide/polycrystalline silicon are already known. In an electrode made of high melting point metal/polycrystalline silicon, the high melting point metal and polycrystalline silicon react in a high temperature heat treatment step after electrode formation, and a high melting point metal solicide layer is generated at the interface. The volume of this nolicide layer is 7
It is thicker than the sum of the volumes of Ricono. Therefore, due to this phenomenon, cracks occur in the high-melting point metal, and the electrode peels off from the underlying silicon oxide film, etc., which are disadvantageous. This phenomenon is also observed when a high melting point metal electrode is directly attached to the silicon substrate. Therefore, in a semiconductor device having a part where a high melting point metal electrode comes into contact with a substrate, the heat treatment temperature during the manufacturing process is usually reduced to about 500°C.
℃ or below, and the high heat resistance, which is an advantage of high melting point metals, can be fully utilized. Electrodes made of high melting point metal silicide/polycrystalline 7-licon do not have such drawbacks and are stable. However, the high melting point metal silicide film
It has the disadvantage that its resistivity is about one order of magnitude higher than that of the same high melting point metal film.
他方、高融点金属を単独で電極や配線に使用すると、酸
化性雰囲気中で温度を上げることができないという欠点
があった。例えば、窒素ガス雰囲気中での７００℃の熱
処理においても、試料を炉に挿入する時に１き込捷れた
微量の酸素によってモリブデンは完Ｐａ５昇華してしま
う。On the other hand, when a high melting point metal is used alone for electrodes or wiring, there is a drawback that the temperature cannot be raised in an oxidizing atmosphere. For example, even in a heat treatment at 700° C. in a nitrogen gas atmosphere, molybdenum is completely sublimed to Pa5 due to the trace amount of oxygen that is injected into the sample when it is inserted into the furnace.
本発明の目的は、したがって、以上述べた欠点を持って
いない高融点金属を含む電極を有する半導体装置を提供
することである。The object of the invention is therefore to provide a semiconductor device having an electrode comprising a refractory metal, which does not have the disadvantages mentioned above.
上記目的を達成するために１本発明による半導体装置は
高融点金属とその高融点金属のシリサイドとから成る二
重層を含む電極を有することを要旨とする。In order to achieve the above object, a semiconductor device according to the present invention has an electrode including a double layer consisting of a high melting point metal and a silicide of the high melting point metal.
本発明の有利な実施の態様においては、上記電極がＭＩ
Ｓ（金属−絶縁膜一半導体）トランジスタのゲート電極
である。In an advantageous embodiment of the invention, the electrode is MI
This is the gate electrode of an S (metal-insulating film-semiconductor) transistor.
本発明の他の一つの有利な実施の態様においては、電極
が半導体基板へのコンタクト電極である。In a further advantageous embodiment of the invention, the electrode is a contact electrode to the semiconductor substrate.
本発明のさらに他の一つの有利な実施の態様においては
、電極が上記二重層と、その下層に設けられた多結晶シ
リコン層とから成る。In a further advantageous embodiment of the invention, the electrode consists of the double layer described above and a layer of polycrystalline silicon below it.
以下に、附図を参照しながら、実施例を用いて本発明を
一層詳しく説明するけれども、それらは例示に過ぎず、
本発明の枠を越えることなく、いろいろの改良や変形が
あり得ることは勿論である。Hereinafter, the present invention will be explained in more detail using examples with reference to the accompanying drawings, but these are merely illustrative.
Of course, various improvements and modifications can be made without going beyond the scope of the present invention.
実施例 １゜
第１図に示すように、シリコン基板１上に素子間分離用
シリコン酸化膜２およびゲート酸化膜６を形成する。つ
ぎに、燐を含有する多結晶７９３７層４、高融点金属シ
リサイド（モリブデン・シリサイド）層５、高融点金属
（モリブデン）層６を形成する。その後、プラズマ・エ
ツチング法によシ、第２図に示すゲート電極７を形成す
る。図は金属−絶縁膜−半導体トランジスタ（以下本明
細書においてはＭｌ、ＳＴと略称する。）を示し、ソー
ス８およびトレーン９はゲート電極７をマスクとして形
成される。ソース８およびドレーン９からの引出し電極
１０はゲート電極７と同様にして形成される。層間絶縁
膜１１およびパノンベーション膜１２は燐硅酸ガラスか
ら成る。Example 1 As shown in FIG. 1, a silicon oxide film 2 for element isolation and a gate oxide film 6 are formed on a silicon substrate 1. Next, a polycrystalline 7937 layer 4 containing phosphorus, a high melting point metal silicide (molybdenum silicide) layer 5, and a high melting point metal (molybdenum) layer 6 are formed. Thereafter, a gate electrode 7 shown in FIG. 2 is formed by plasma etching. The figure shows a metal-insulating film-semiconductor transistor (hereinafter abbreviated as M1, ST), and a source 8 and a train 9 are formed using the gate electrode 7 as a mask. Extracting electrodes 10 from the source 8 and drain 9 are formed in the same manner as the gate electrode 7. The interlayer insulating film 11 and the pannonvation film 12 are made of phosphosilicate glass.
本発明に用いる高融点金属ノリサイド層は高融点金属と
７リコンの同時または連続蒸着法、気相成長法、スパッ
タ法、等によって形成され、その厚さは１〜３Ｑｎｍ程
度が適切である。The high melting point metal nolicide layer used in the present invention is formed by simultaneous or continuous vapor deposition of a high melting point metal and silicon, vapor phase growth, sputtering, etc., and its thickness is suitably about 1 to 3 Q nm.
以上述べた多結晶シリコン層−高融点金属ンリザイド層
−高融点金属層の６層から成る電極は５００℃以上の熱
処理工程を経ても電極がわれたりはがれたすせず、かつ
低い電気抵抗を有している。The electrode consisting of the six layers of polycrystalline silicon layer, high melting point metal resin layer, and high melting point metal layer described above does not crack or peel off even after a heat treatment process of 500°C or higher, and has low electrical resistance. are doing.
実施例 ２゜
第６図を参照すればシリコン基板１に素子間分離用／リ
コン酸化膜２、ゲート酸化膜６、高融点金属（モリブデ
ン）のゲート電極１３、層間絶縁膜１１、ソース８、ド
レーン９、コンタクト孔１４を形成後、スパッタ法によ
ってｉＱ ｎｍの厚さの高融点金属シリサイド（モリブ
デン・ノリサイド）層５、そして連続的に２００ ｎｍ
の厚さの高融点金属（モリブデン）層６を形成する。つ
ぎに、第４図に示すように、プラズマ・エツチングによ
って引出し電極１５に加工し、パンシベーション膜１２
を被着し、ＭＩＳＴを形成する。Embodiment 2゜Referring to FIG. 6, a silicon substrate 1 is provided with an element isolation/recon oxide film 2, a gate oxide film 6, a gate electrode 13 made of a high melting point metal (molybdenum), an interlayer insulating film 11, a source 8, and a drain. 9. After forming the contact hole 14, a high melting point metal silicide (molybdenum silicide) layer 5 with a thickness of iQ nm is formed by sputtering, and then a layer of 200 nm is continuously formed.
A high melting point metal (molybdenum) layer 6 is formed to have a thickness of . Next, as shown in FIG. 4, the lead electrode 15 is processed by plasma etching, and the pansivation film 12 is
is deposited to form MIST.
以上のように形成したＭＩＳＴにおいては、５００゜℃
以上の高温熱処理を経た場合でも、電極がはがれるとい
う事故は生じなかった。なお、高融点金属シリサイド層
は１〜５Ｑ ｎｍ程度の厚さでよい。In the MIST formed as described above, the temperature was 500°C.
Even after the above-described high-temperature heat treatment, no accident of electrode peeling occurred. Note that the high melting point metal silicide layer may have a thickness of about 1 to 5 Q nm.
まだ、高融点金属シリサイド層は高融点金属とシリコン
の同時あるいは連続蒸着法、気相成長法、スパック法、
等どのような方法によって形成されてもよい。なお、本
実施例のＭＩＳＴのゲート電極としては、八４や多結晶
シリコン等の他の導体を用いて形成することもできる。However, the refractory metal silicide layer can still be produced by simultaneous or sequential deposition of refractory metal and silicon, vapor phase epitaxy, spuck method,
It may be formed by any method. Note that the gate electrode of the MIST in this embodiment can also be formed using other conductors such as 84 or polycrystalline silicon.
実施例 ６゜
高融点金属からなる電極や配線表面に高融点金属シリサ
イド層を被覆しておけば、電極や配線の酸化を防止する
ことができる。Example 6: Oxidation of the electrodes and wiring can be prevented by coating the surfaces of the electrodes and wiring made of a high-melting point metal with a high-melting metal silicide layer.
高融点金属ソリサイドは高温酸化処理によって表面にノ
リコン酸化膜が形成され、この酸化膜が高融点金属の耐
酸化効果を持つ。なお、この酸化膜は通常の／リコン酸
化膜エツチング液で除去することができる。High-melting point metal solicide has a Noricon oxide film formed on its surface through high-temperature oxidation treatment, and this oxide film has the oxidation-resistant effect of a high-melting point metal. Note that this oxide film can be removed with a normal/recon oxide film etching solution.
第５図を参照すれば、シリコン基板１上に素子間分離用
シリコン酸化膜２、ゲート酸化膜６を形成した後、２０
０ ｎｍ厚の高融点金属（モリブデン）層６、高融点金
属シリサイド（モリブデン・シリサイド）層５を連続し
て形成する。ついで、第６図に示すように、プラズマ・
エツチングによってゲート電極１６を形成し、続いてイ
オン打込みによってソース８およびドレーン９、燐硅酸
ガラスの層間絶縁膜１１、コンタクト孔１４を形成する
。Referring to FIG. 5, after forming a silicon oxide film 2 for element isolation and a gate oxide film 6 on a silicon substrate 1,
A refractory metal (molybdenum) layer 6 and a refractory metal silicide (molybdenum silicide) layer 5 having a thickness of 0 nm are successively formed. Next, as shown in Figure 6, the plasma
A gate electrode 16 is formed by etching, and then a source 8, a drain 9, an interlayer insulating film 11 of phosphosilicate glass, and a contact hole 14 are formed by ion implantation.
つぎに、コンタクト孔が開いている部分のみ不純物拡散
層が深くなるように高温で燐を拡散し、深いソース８′
および深いトレー７９′を作る。この燐拡散工程は酸化
雰囲気であるため、ゲート電極１６のコンタクト部分の
高融点金属シリサイド表面にシリコン酸化膜１７が形成
され、拡散工程中の高融点金１の昇華を阻止する。この
シリコン酸化膜１７を弗酸系エツチング液で除去した後
、第７図に見るように、アルミニウムの引出し電極１８
、パノ／ベーション膜１２を形成してＭＩＳＴを作成す
る。Next, phosphorus is diffused at high temperature so that the impurity diffusion layer becomes deep only in the area where the contact hole is opened, and the deep source 8'
and make a deep tray 79'. Since this phosphorus diffusion process is performed in an oxidizing atmosphere, a silicon oxide film 17 is formed on the high melting point metal silicide surface of the contact portion of the gate electrode 16 to prevent sublimation of the high melting point gold 1 during the diffusion process. After removing this silicon oxide film 17 with a hydrofluoric acid etching solution, as shown in FIG.
, a pano/vation film 12 is formed to create a MIST.
高融点金属シリサイド層は、上記の燐拡散工程以外の窒
素アンニール、燐硅酸ガラス被着工程においても、高融
点金属の昇華防止に役立つ。The high melting point metal silicide layer also helps to prevent sublimation of the high melting point metal in nitrogen annealing and phosphosilicate glass deposition steps other than the above-mentioned phosphorus diffusion step.
以上説明した通り、本発明による半導体装置は酸化性雰
囲気中においても高い温度に耐え、高融点金属を含む電
極がわれたり、はがれたりすることば々く、かつ低い電
気抵抗を持つという長所を有する。As explained above, the semiconductor device according to the present invention has the advantage that it can withstand high temperatures even in an oxidizing atmosphere, that electrodes containing high melting point metals often break or peel off, and that it has low electrical resistance.
第１図および第２図は本発明の第１の実施の態様におけ
る半導体装置の製造工程を示す断面図、第３図および第
４図は本発明の第２の実施の態様における半導体装置の
製造工程を示す断面図、第５図、第６図および第７図は
本発明による第３の実施の態様における半導体装置の製
造工程を示す断面図である。
１・・／リコン基板
２・・素子間分離用シリコン酸化膜
６・・ケート酸化膜 ４ ・多結晶シリコン層５・
高融点金属シリサイド層
６・高融点金属層
７．１ろ、１６・ ゲート電極
８．８・・ノース ９．９・・・ドレーン１０．
１５．１８・・引出し電極
１１・・層間絶縁膜
１２・・パノ／ベーション膜
１４・・コンタク＋一孔１７・・ンリコン酸化膜代理人
弁理士 中利純之助
先 １ 図
大 ２ 図
５ ６ １ ソ７Ｉ７３
［Ｚｌ
Ａ７４［２］
１４８ ３Ｃ）
１？５図
８’８３９９’1 and 2 are cross-sectional views showing the manufacturing process of a semiconductor device according to a first embodiment of the present invention, and FIGS. 3 and 4 are sectional views showing the manufacturing process of a semiconductor device according to a second embodiment of the present invention. 5, 6, and 7 are cross-sectional views showing steps for manufacturing a semiconductor device according to a third embodiment of the present invention. 1.../Recon board 2... Silicon oxide film for isolation between elements 6... Kate oxide film 4 ・Polycrystalline silicon layer 5 ・
High melting point metal silicide layer 6, high melting point metal layer 7.1, 16, gate electrode 8.8, north 9.9, drain 10.
15.18...Extracting electrode 11...Interlayer insulating film 12...Pano/bation film 14...Contact+one hole 17...Nlicon oxide film Patent attorney Junnosuke Nakatoshi Address 1 Figure 2 Figure 5 6 1 So 7I73
[Zl A74[2] 148 3C)
1?5 Figure 8'8399'
Claims (1)
から成る二重層を含む電極を有することを特徴とする半
導体装置。 （２）上記電極がＭＴＳ（金属−絶縁膜一半導体）トラ
ンジスタのゲート電極であることを特徴とする特許請求
の範囲第１項による半導体装置。 （ロ）上記電極が半導体基板へのコンタクト電極である
ことを特徴とする特許請求の範囲第１項による半導体装
置。 （４）上記電極は上記二重層の下層に設けられた多結晶
シリコン層をさらに含むことを特徴とする特許請求の範
囲第１項、第２項まだは第６項のいずれか一つによる半
導体装置。[Scope of Claims] (1) A semiconductor device characterized by having an electrode including a double layer consisting of a high melting point metal and a silicide of the high melting point metal. (2) The semiconductor device according to claim 1, wherein the electrode is a gate electrode of an MTS (metal-insulator-semiconductor) transistor. (b) The semiconductor device according to claim 1, wherein the electrode is a contact electrode to a semiconductor substrate. (4) The semiconductor according to any one of claims 1, 2, and 6, wherein the electrode further includes a polycrystalline silicon layer provided below the double layer. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10938483A JPS5910271A (en) | 1983-06-20 | 1983-06-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10938483A JPS5910271A (en) | 1983-06-20 | 1983-06-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5910271A true JPS5910271A (en) | 1984-01-19 |
Family
ID=14508868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10938483A Pending JPS5910271A (en) | 1983-06-20 | 1983-06-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5910271A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60225475A (en) * | 1984-04-23 | 1985-11-09 | Mitsubishi Electric Corp | Semiconductor device |
| JPS6132476A (en) * | 1984-07-23 | 1986-02-15 | Sharp Corp | Semiconductor device |
| JPS6132477A (en) * | 1984-07-23 | 1986-02-15 | Sharp Corp | Manufacture of semiconductor device |
| JPS6182479A (en) * | 1984-09-28 | 1986-04-26 | Sharp Corp | Manufacture of semiconductor device |
| US6197702B1 (en) | 1997-05-30 | 2001-03-06 | Hitachi, Ltd. | Fabrication process of a semiconductor integrated circuit device |
| US7049187B2 (en) | 2001-03-12 | 2006-05-23 | Renesas Technology Corp. | Manufacturing method of polymetal gate electrode |
| US7053459B2 (en) | 2001-03-12 | 2006-05-30 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for producing the same |
| US7221056B2 (en) | 2003-09-24 | 2007-05-22 | Renesas Technology Corp. | Semiconductor integrated circuit device and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4926462A (en) * | 1972-07-04 | 1974-03-08 | ||
| JPS4940859A (en) * | 1972-08-25 | 1974-04-17 | ||
| JPS5612754A (en) * | 1979-06-11 | 1981-02-07 | Gen Electric | Composite structure and method of forming same |
-
1983
- 1983-06-20 JP JP10938483A patent/JPS5910271A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4926462A (en) * | 1972-07-04 | 1974-03-08 | ||
| JPS4940859A (en) * | 1972-08-25 | 1974-04-17 | ||
| JPS5612754A (en) * | 1979-06-11 | 1981-02-07 | Gen Electric | Composite structure and method of forming same |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60225475A (en) * | 1984-04-23 | 1985-11-09 | Mitsubishi Electric Corp | Semiconductor device |
| JPS6132476A (en) * | 1984-07-23 | 1986-02-15 | Sharp Corp | Semiconductor device |
| JPS6132477A (en) * | 1984-07-23 | 1986-02-15 | Sharp Corp | Manufacture of semiconductor device |
| JPS6182479A (en) * | 1984-09-28 | 1986-04-26 | Sharp Corp | Manufacture of semiconductor device |
| US6987069B2 (en) | 1997-05-30 | 2006-01-17 | Hitachi, Ltd. | Fabrication process of a semiconductor integrated circuit device |
| US6503819B2 (en) | 1997-05-30 | 2003-01-07 | Hitachi, Ltd. | Fabrication process of a semiconductor integrated circuit device |
| US6528403B2 (en) | 1997-05-30 | 2003-03-04 | Hitachi, Ltd. | Fabrication process of a semiconductor integrated circuit device |
| US6784116B2 (en) | 1997-05-30 | 2004-08-31 | Hitachi, Ltd. | Fabrication process of a semiconductor integrated circuit device |
| US6197702B1 (en) | 1997-05-30 | 2001-03-06 | Hitachi, Ltd. | Fabrication process of a semiconductor integrated circuit device |
| US7122469B2 (en) | 1997-05-30 | 2006-10-17 | Hitachi, Ltd. | Fabrication process of a semiconductor integrated circuit device |
| US7049187B2 (en) | 2001-03-12 | 2006-05-23 | Renesas Technology Corp. | Manufacturing method of polymetal gate electrode |
| US7053459B2 (en) | 2001-03-12 | 2006-05-30 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for producing the same |
| US7144766B2 (en) | 2001-03-12 | 2006-12-05 | Renesas Technology Corp. | Method of manufacturing semiconductor integrated circuit device having polymetal gate electrode |
| US7300833B2 (en) | 2001-03-12 | 2007-11-27 | Renesas Technology Corp. | Process for producing semiconductor integrated circuit device |
| US7375013B2 (en) | 2001-03-12 | 2008-05-20 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for manufacturing the same |
| US7632744B2 (en) | 2001-03-12 | 2009-12-15 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for manufacturing the same |
| US7221056B2 (en) | 2003-09-24 | 2007-05-22 | Renesas Technology Corp. | Semiconductor integrated circuit device and manufacturing method thereof |
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