JPS5857772B2 - Analog data processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing system in which an analog input signal is converted into a digital signal, stored or processed, and this digital signal is sent out again as an analog output signal.

There is a need for an automatic recording device or other device that provides an analog input signal with a delay of several seconds or performs various calculations and then provides an output as an analog signal.

Figure 1 shows an automatic recording device that is an example of its use.
This figure shows how five pens P1 to P5 perform recording according to their input signals when the recording paper moves slowly at a constant speed (2) in the direction of the arrow in the figure.

At this time, each of the pens P1 to P5 is deviated by l with respect to the moving direction of the recording paper, so if the recording paper is examined later, a shift will occur in the time relationship.

Therefore, in order to match this time relationship, it is necessary to give a delay to the input signal for each channel of each pen P1 to P5.

The amount of delay is 41. for pen P5. /
31/■ for the V pen P4, 21/■ for the V pen P3, 7/7 for the V pen P2, and 0 for the V pen P1.

Here, ■/l ranges from 1 second to several tens of seconds, so it is difficult to perform this signal processing in analog.After converting it to a digital signal and processing it with a digital data processing device, the analog signal is converted back into a digital signal. It will be converted and output.

For this reason, each channel has an analog digital signal (hereinafter referred to as rADJ).

) conversion circuit and digital analog (hereinafter referred to as rDAJ).

) It is necessary to have a conversion circuit.

Moreover, in many cases, the input signal is at a floating potential, and a common ground cannot be established, which complicates the circuit.

This has the disadvantage that the device is expensive.

The present invention improves this by simplifying the circuit configuration and
The purpose is to make equipment economical.

The present invention makes the circuit more economical by commonly using the circuit main parts of the above-mentioned AD conversion circuit and DA conversion circuit.

In other words, since the digital data processing device can perform advanced processing, the data processing device is configured to perform switching control of the AD conversion/DA conversion of the circuit, and the switching circuit controlled by this is a feature. do.

This will be explained in more detail with reference to the drawings.

FIG. 2 is a block diagram of the entire apparatus according to the embodiment of the present invention.

In the diagram, AI is analog input, AO is analog output, and CVT
denotes a conversion circuit, each of which is independently provided for n channels.

Each conversion circuit CVT has a common digital data processing device C.
Connected to PU.

In such a system, the analog input signal AI of each channel is converted into a digital signal by the conversion circuit CVT, sent to the data processing unit CPU, subjected to appropriate processing, and then converted back to an analog signal by the conversion circuit cVT. It is converted and sent out as an analog output signal AO.

Processing in the data processing device CPU includes delays and various calculations.

FIG. 3 is a diagram showing one configuration example of the conversion circuit CVT.

AI indicates an analog input signal terminal, and AO indicates an analog output signal terminal.

DI is a digital input, CK is a clock input, EOC is a control output, and DO is a device output, each of which is connected to the data processing device CPU described above.

Since this conversion circuit CVT is set to a floating potential for each channel, the ground is connected to the data processing device CPU.
and independent.

Therefore, each input/output DI. CK, EOC and DO are isolated by photocoupler PC and connected to conversion circuit CV.
It is connected to each circuit of T.

The digital input DI is connected to two D-type flip-flops F.
It is guided to a switching circuit consisting of F.

It is also branched and connected to the input of gate G2.

Two flip-flops FF are connected in series, and their output Q2 is given to the conversion start input SC of the register REG.

The clock power CK is connected to the clock power CK of the register REG and the input of the game hG, via a Schmitt circuit SH.

Gate G4 is a NOR gate with control signal r6, and its output clock EOC-CK is connected to the above two flip-flops F.
It is supplied to F.

Serial output 5OUT of register REG is connected to digital output Do.

Analog input AI is connected to the input of comparator circuit COMP.

The output of this comparison circuit COMP is connected to the input of gate G1.

Gate G1 and gate G2 are flip-flop F
F's outputs Q1 and Ql alternately open and close both gates 1-G.

The outputs of G2 and G2 are combined by gate G3 (NAND) and connected to the digital output of register REG.

The contents of register REG are changed to DA by conversion start input SC.
The signal is configured to be applied to the conversion circuit DA.

The output of this DA conversion circuit DA is coupled to the input of an inverting amplifier A1.

The output of this inverting amplifier A1 is connected to one input of the comparator circuit COMF, and is led to an analog output terminal AO via a switch SW whose opening and closing are controlled by a control signal EOC, and further via a CR filter. ing.

The operation of the apparatus configured as described above will be explained using the waveform diagram shown in FIG.

In this example, the period T is 1 to 16, which is one period. For example, if AD conversion is performed in the first period and DA conversion is performed in the next period, the operation will be as follows.

Whether AD conversion or DA conversion is to be performed is indicated by a digital signal from the aforementioned data processing device CPU.

In the example shown here, it is configured to be identified by the first 3 bits that arrive at the digital input DI, and if the first 3 bits are rloooJ, it is AD conversion; if it is "111", it is DA conversion.

This is identified by two flip-flops FF.

In other words, if the first 3 bits are l-100J, the fourth
As shown in the upper part of the figure, the signal Q1 once rises, falls, and in its place, the signal Q2 rises and immediately falls.

If the signal is "111", the signal Q1. Q2 is continuously “
1".

This signal Q (and its inverted signal Ql) controls gates G1 and G2, and signal Q2 controls conversion start SC.

When AD conversion is now commanded, the data of the successive approximation AD conversion is input to the register REG from the output of the comparator COMP.

In this successive approximation AD conversion, as is known, when the conversion register receives a conversion start SC, it performs DA conversion from the MSB side and compares it with the input, and the output of the comparison circuit COMP is inverted depending on the magnitude.

While this is left as it is as information or is reset to return to zero, the conversion is completed sequentially until the LSB is reached.

On the other hand, when DA conversion is commanded, digital data is input to the input of register REG.

This data is temporarily held in the register REG, supplied to the DA conversion circuit DA, and converted into an analog signal.

The digital output signal Do is taken into the data processing device CPU, temporarily stored, given a predetermined delay, and if necessary, subjected to calculations such as display scale conversion, and returned to the conversion circuit CTV as the digital input signal DI. .

This delay and calculation corrects the misalignment of each pen as explained in FIG. 1, for example.

In this way, it is possible to share the register REG and the DA conversion circuit DA for AD conversion and DA conversion.

When the conversion is completed, the two flip-flops FF are reset and have the next input.

Note that while the conversion is being executed, the analog output is disconnected from the output of the DA conversion circuit DA, and operates to hold the previous value.

As described above, according to the present invention, the main parts of the circuit can be used in common for AD conversion and DA conversion, making the circuit simpler and more economical.

Since the device of the present invention can adopt floating grounding and can also be controlled through digital input, it has excellent effects when implemented in automatic recording devices and the like.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an automatic recording device shown as an example of a usage form of the present invention. FIG. 2 is a configuration diagram of an embodiment of the present invention. FIG. 3 is a configuration diagram of the main parts of the apparatus according to the embodiment of the present invention. FIG. 4 is an operational waveform diagram of the device of the above embodiment.

Claims (1)

[Claims] 1. Converting an analog input signal into a digital signal, importing this digital signal into a digital data processing device, processing it, converting the processed signal back into an analog signal, and sending it out as an analog output signal. In a data processing method, a conversion circuit corresponding to the number of analog input signals is provided, and between the conversion circuit and the digital data processing device, a serial digital signal is transmitted from the conversion circuit to the digital data processing device. A first signal line is connected to a second signal line for transmitting a serial digital signal from the digital data processing device to the conversion circuit, and the digital data processing device transmits a serial digital signal to the second signal line. The conversion circuit is configured to give a command to the conversion circuit as to whether to perform AD conversion or DA conversion using a specified plurality of bits at the beginning of a series of digital data, and the conversion circuit determines whether the specified plurality of bits are for AD conversion or DA conversion. A circuit is provided to identify whether the command is an AD conversion, and when the command identified by this circuit is an AD conversion, the analog input signal is converted to a digital signal and sent to the first signal line, and the command is converted into a digital signal. In the case of conversion, the digital signal that arrives on the second signal line following the specific plurality of bits is configured to be converted into an analog signal and sent as an analog output signal, and further, the conversion circuit is configured to a comparison circuit which inputs an input signal to one side; and an output of the discrimination circuit which selects the output of the comparison circuit when the command is AD conversion, and selects the output of the comparison circuit when the command is AD conversion, and selects the second signal when the command is DA conversion. A circuit for identifying the above, comprising a gate circuit for selecting a digital signal arriving on a line, a register for temporarily accumulating the output signal of this gate circuit, and a digital-to-analog conversion circuit for converting the parallel output of this register into an analog signal. When the command is AD conversion, the digital signal obtained by successive comparison by the loop of the register, the digital/analog conversion circuit, and the comparison circuit and accumulated in the register is transferred from the serial output of the register to the digital signal. The parallel output of the register is sent as a digital signal output to the first signal line, and when the command is DA conversion by the output of the identifying circuit, the parallel output of the register is converted into an analog signal. An analog data processing method characterized in that it is configured to be sent as an output. 2. The analog data processing system according to claim 1, wherein the first signal line and the second signal line are isolated from the ground of the analog signal of each conversion circuit.