JPS5851557A - Large scale integrated circuit device - Google Patents

Abstract

PURPOSE:To effectively increase the number of gates without increasing the size of a chip by forming a logic element under a wiring channel region and connecting the element to the prescribed cell. CONSTITUTION:Many unit cell rows 2, 3, ... of, for example, C-MOS structure are arranged at the prescribed interval on an IC chip 1, with the space at the interval as a wiring channel 6. A logic element 30 such as an inverter or the like is provided on a semiconductor substrate directly under the channel 6. Elements (e.g., a depletion mode load MOSFET, an enhancement mode driver MOSFET) provided on the element 30 are connected to wirings (e.g., a power source line 14, an output line 15, an input line 23 and the like) on the channel region 6, and are connected through the wirings to the prescribed logic elements (NAND gate, an inverter and the like) in the respective cell rows 2, 3.

Description

[Detailed description of the invention] The present invention relates to large scale integrated circuit devices, particularly OMO8.

(complementary MO8) Logic LSIK
It is related to

When configuring 0M08 logic in this type of random logic LSI, a large number of 0MO8 logic cell columns are arranged at predetermined intervals, and a predetermined arrangement is applied to the wiring channel region provided within each function. Connections between cell rows and between individual cells create one unified system function. In this case, when it is desired to add a logic gate, for example an inverter, the logic element in the cell cannot be used as an inverter because the number of darts in the logic cell is limited. Therefore, the load MO8 for the inverter and the driver MO2 are placed in an area different from 0M08.
However, it has been found that this increases the chip area and makes it impossible to reduce the chip size.

Moreover, if this inverter is configured with 0MO8,
Since the pair of loads MO8 and )247MO8 need to be placed in close proximity from a structural point of view, a certain area must be secured for their arrangement, and the degree of freedom in arrangement is small, and the element size itself is also limited. I know it will be relatively large.

Therefore, an object of the present invention is to provide a logic L8I in which the number of gates is effectively increased without increasing the chip size.

In order to achieve this objective, the present invention focuses on the fact that the wiring channel region between cell columns occupies a considerable area within a chip. A MOS of one conductivity type channel is formed and connected to a predetermined cell by 5C.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
'' Figure 1 shows the layout of the main parts of the large-scale random logic.The IO chip 1 has 0M0
Numerous unit cell rows with 8 structure 2゜3.4.5...
... are arranged at predetermined intervals, and the wiring channel region 6 is located within the interval. Further, a common N-[PfJ well 8 shown by a virtual line in the semiconductor substrate 26 is formed between adjacent cell columns, and each logic cell included in this well has an N-channel MI as a logic gate.
8FET (Metal In5ulator 8
amiconductor FieldEffect
Translstor) parts 2a, 3m, 4a.

Sm... is provided. Each logic cell on the substrate outside well 8 also has a P-channel MII9FffT that forms a logic gate in pair with the N-channel MI8FET.
Sections 2b, 3b, 4b, 5b, . . . are provided. Note that in the drawing, some cells in the cell row 2.3 are shown separately, but other cells are also arranged in the same way, so they are shown in a simplified manner.

What should be noted here is that in the wiring channel region 6, there is an inverter etc. on the semiconductor substrate directly below it! Element portions 30, 31, etc. are provided and are connected to each magnetomotive force on the K wiring channel region 6 as described later, and are connected to predetermined logic elements in each cell column (such as NAND gates, etc.). (inverter) K connection.The logic elements N530 in well 8 are all composed of N-channel MI8FBT,
On the other hand, the logic 311 resistor section 31 provided on the N-5 substrate 26 is entirely composed of P-channel MIspg'r.
Each channel is composed of a JIL-conductivity type channel (single channel). Below, the N-channel MI in well 8
Although the 8FI8T will be mainly explained, the P-channel MI 8FET on the substrate 1 is also similar.

FIG. 2 shows a state in which an inverter is provided in the P-type well 8 under the wiring channel region 6.

That is, in the P-type well 8, an N"ffi diffusion region 9.10 for a depletion mode load MOS is formed as a source or drain region, and an N+ warm diffusion region 11 for an enhancement mode dry node MOS is formed. .12
is formed as a source or drain region. The drain region lO of the load MO8 has an aluminum arrangement ll 3
Due to the power supply voltage VCC supply supply element arrangement ll
4, the source region 9 is connected to the output line 15KW! by an aluminum wiring 915Kll for output extraction, and the polysilicon gate electrode 16 is connected to the output line 15KW by an aluminum wiring 17. It is threaded. On the other hand, in the dry <MOS, the drain region 12 is connected to the output line 15 common to the load MO8 through the aluminum wiring @isK, and the source region 11 is connected to the ground level aluminum wiring 20Klll by the aluminum wiring 19. The polysilicon gate electrode 21 has an Al=U arrangement @22f
It is connected to the aluminum wiring @23 for input signal supply from the IC. Then, a part of the human input signal line 23 of this sysoglu channel λ is connected to the logic cell column 3 from the aluminum wiring 24 (multilayer wiring structure 02nd layer Al=Um) K.
For example, the output terminal Kljl of a cell such as an inverter is wired, while the output line 15 is wired with aluminum wire @ZS (same as 2
For example, 2 of the other logic cell column 2 is
It is connected to the input terminal of the human-powered NAND gate. Note that the P-channel load MO8 and driver MO8 (10 in Figure 1) provided on the base 1 [7m body] may be similarly configured and may be similarly KII-wired in a predetermined cell.

In this way, by utilizing the wiring channel region 6 and providing a logic element, such as an inverter, loaded with a depletion mode MOS, and connecting this to a predetermined cell in the cell string, the chip size can be increased. It becomes possible to increase the number of logic gates without increasing the number of logic gates. reverse VC
*The advantage is that if the number of gates is kept the same, the chip size can be reduced.
I can be made smaller.

In addition, since both the load MO& and the driver MO8 described above are single channels, they can be provided at any location in the wiring channel region, and these MOII can be set to 0 MO.
It is not necessary to arrange both MOBs close to each other as in the case of configuring with 8 MOBs. Follow [, with increased flexibility in placement, 0M
The element size itself can also be made smaller compared to 08. Note that in this embodiment, each cell row is configured with 0 MO8, so power consumption can be reduced in this respect, but since the load MO8 and driver MO8 described above have a constant power of negative 5%, For LaI that is actually applied, it is desirable to be able to tolerate an increase in the power consumption of Il&, so the structure according to this embodiment is suitable for products that can tolerate an increase in power consumption. By reducing the chip size and mixing it with the logic circuit that can be realized for the first time with KOMO8, it is possible to create a small logic circuit.
This makes it possible to obtain an IC at low cost.

In addition, since the load MO8 mentioned above is in the depressin mode, the well-known ion implantation technique #tK allows channel II
K ion implantation is performed to lower the threshold voltage ■th. Furthermore, in practice, any number of logic elements such as the load MO8 and the driver MO8 described above can be provided at desired locations in the wiring channel region, and the number of gates to be added can be determined depending on the purpose.

Figure 3 shows the above logic element 1130 and the 0M
083 is shown. This cross section is shown in ↓5, where the contact portion with the aluminum wiring is exposed, in order to facilitate understanding of the structure of each element part.

26 is an N"[1 silicon substrate, 27 is a field 8iO1 film, 28 is a gate oxide film, 29 is a surface oxide film of a polysilicon film, and 45 is a phosphosilicate glass film.0MO8, for example, an inverter. 3 is an N-channel MI8F consisting of N++ source regions 32 and 33 formed in the well 8 and a polysilicon gate electrode 34.
ET and the P''ll source region 35 and drain region 36 formed on the base [26 itself] and the polysilicon gate electrode 3.
7 and P channel MI8FiilT. An input signal is applied to each gate electrode 4ii34.17, and an output is taken from the aluminum arrangement 138 connecting the P+ field region 36 and the N+ field region 32. Further, the p+■ region 35 is grounded by the aluminum arrangement 11m9, and the N'' layer region 33 is grounded by the aluminum arrangement 140.
The power supply (Vcc) is connected.

Next, a method for manufacturing the device shown in FIG. 3 will be explained in Section 4m.

First, as shown in Figure 4A, on one main surface of the N'''' type substrate 26,
A Plil field, a film 27, and a gate oxide film 28 are formed using a known diffusion technique 9, selective oxidation technique, or the like. Although not shown, the logic element section 3
MO8111 in depressing mode is shallowly implanted with arsenic, etc. in advance, and the load M formed there is
Lower the ■th of OB [oh(.

Next, the entire I
iK polysilicon is grown and subjected to a known phosphorus treatment and patterned by photoetching to form polysilicon films 16, 21.degree. 34.37 in the shape of each gate electrode, respectively.

Next, as shown in FIG. 40, after a light treatment is performed in a thermal oxidizing atmosphere to form an atO film 29 on the surface EI of each polysilicon film, the area other than the well 8 is covered with a mask 41.

As this mask 41, a photoresist patterned by known exposure and in-situ processing may be used. Then, the entire surface is irradiated with a phosphorus or arsenic ion beam 42, and ions are selectively implanted through the Quell SK gate oxide film 28 not covered with the mask 41. At this time, field 840, film 2F and polysilicon film 16, 21.34
Since also has a masking effect, each of the N''jll regions 9°1G, 11, 12, 32, and 33 are formed in a self-aligned manner (by self-line method).

Next, as shown in FIG. 4D, this time only the top of the well 8 is covered with a mask 43 similar to the above, and a boron ion beam 44 is irradiated to gate oxidize I[ on both sides of the polysilicon L[370].
selectively implanting boron through 28, thereby
The P+ territory area 3536 is based on the self-line method [26
Form each.

Next, in step 48@5, a phosphosilicate glass film 46 is deposited on the entire surface by OVD, and this glass film 4s and the underlying gate oxide film 28 are sequentially etched [, and each contact hole 46, 47.48° 4G , 50, 51.52.
53 are formed respectively.

Furthermore, aluminum was deposited on the entire surface using Omichi's vacuum evaporation technology, and each aluminum layer of 8113.15.1g as shown in Figure 3 was made using Omichi's photo etching.

Pattern to 19.318, 39.40#.

According to this manufacturing method, an additional logic gate can be easily formed in the semiconductor substrate under the wiring channel region without substantially changing the normal manufacturing process.

Although the present invention has been exemplified above, the above-described embodiments can be made even larger based on the technical concept of the present invention.

For example, the cell columns described above may be summed to form logic in a master slice manner, or may be summed to form logic in a non-master slice manner.

tft1 The present invention can be applied to various types of L8I, and in some cases L8IK for trains, non-synthesizers, etc.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, and FIG. 1 is a plan view showing the layout of the logic L8I for the main J11 section, and FIG. 2 shows the connection relationship between the gate of the wiring channel region and the gate of the cell column. 4A to 4E are sectional views sequentially showing the manufacturing process of the structure shown in FIG. 3. In addition, in the symbols used in the drawings, 2 to 5 are logic cell columns, 6 is a wiring channel region, 8 is a Pal well,
13 to 15, 17 to 20 and 22 to 25 are aluminum wirings, 26 is an N-type substrate, and 30 and 31 are logic element portions. Figure 1 Figure 2

Claims (1)

[Claims] 1. In a large-scale integrated circuit device in which a wiring channel region is provided between logic cell columns, a logic element is formed on a semiconductor substrate under the wiring channel region, and this logic element is connected to the wiring channel region. A large-scale integrated circuit device in which a region is arranged 5IKIi[+] and is connected to a predetermined cell in the logic cell column via this wiring.