KR920005798B1 - Borderless master slice semiconductor device - Google Patents

Abstract

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Description

Borderless master slice semiconductor device

1 is a plan view of a conventional gate array master wafer.

2 is an enlarged configuration diagram of a conventional gate array master chip.

3 is a plan view of a gate array master wafer according to the present invention.

4 is an enlarged plan view of a portion A of FIG.

5 is a plan view of the gate array master wafer after the master chip according to the present invention is formed.

6 is an enlarged plan view of part S of FIG.

* Explanation of symbols for main parts of the drawings

1: wafer 2: master chip

3: internal logic circuit forming area 4: bonding pad forming area

5: Cell array area 6: I / O cell area

7: bonding pad 10: basic cell

20: well area 21: second conductivity type MOS transistor

22: first conductivity type diffusion region 30: intermediate region

31: first conductivity type MOS transistor 32: second conductivity type diffusion region

40: bonding pad 50: scribe line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice semiconductor device, and more particularly, to a borderless master slice semiconductor device capable of freely setting the size of a master chip by forming an independent basic cell structure on a front surface of a wafer.

In general, a master slice or gate array semiconductor device is a design method in which basic elements such as transistors are regularly arranged on a master chip of a predetermined standard and are customized only by a wiring process.

The conventional gate array master chip 2 of FIG. 2 has an internal logic circuit forming area 3 having a cell array area 5 at its center and an input / output cell area 6 around it, and the input / output cell area 6 ), The size of the master chip 2 is fixed since the bonding pad forming region 4 is formed around the pad 7. However, the size or area of the chip is determined by the number of gates contained therein, and the supplier is to prepare different master wafers divided by the number of gates. Therefore, a semiconductor device is manufactured through a wiring process for a gate array having a size corresponding to an individual customized product or larger than that. Therefore, since the size of the conventional gate array is standardized, it is difficult to design the optimum chip size to meet the demand of the orderer, and there is a need to manage the production and the product according to the standard. In addition, only limited devices prepared in standardized chips can be used, resulting in a low degree of freedom in circuit design.

Accordingly, an object of the present invention is to provide a borderless master slice semiconductor device that can freely set the size of the master chip to the desired size corresponding to the order of the order to solve the problems of the prior art as described above.

Another object of the present invention is to provide a borderless master slice semiconductor device capable of unifying the production process of the gate array semiconductor device and simplifying the product management.

According to the present invention, a borderless master slice semiconductor device includes a plurality of first conductive independent well regions arranged in a row direction on a front surface of a semiconductor wafer, and a plurality of second conductive intermediate regions arranged in a row direction between these independent well regions. Equipped with. In the first conductive well regions, a plurality of second conductive MOS transistor groups are arranged in a row direction, and a first conductive diffusion region is disposed on both sides of each of the second conductive MOS transistor groups. It is. In the second conductive intermediate region, a plurality of first conductive MOS transistor groups are formed in the row direction corresponding to the second conductive MOS transistor groups. A plurality of second conductive diffusion regions are formed on both sides of each of the first conductive MOS transistor groups described above.

As described above, the basic cells including the independent well region arranged in the matrix form on the front surface of the wafer and the transistor group formed in the intermediate region and the diffusion regions arranged on the left and right sides thereof are independent of each other. Even if the transistor region is cut off, the transistor group constituting the master chip becomes electrically stable. Therefore, it is possible to freely and optimally set the size of the master chip for any application circuit.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 3 is a plan view of the gate array master wafer according to the present invention, and FIG. 4 is an enlarged plan view of part A of FIG.

In FIG. 4, reference numeral 10 denotes a basic cell of a CMOS gate array according to the present invention, which is composed of an independent well region 20 and a well region of another basic cell longitudinally adjacent to the well region 20. It has an intermediate region 30 which exists in between.

The independent well region 2 is composed of a conductive material different from the material of the semiconductor wafer (here, referred to as a second conductive member) (herein referred to as a first conductive member), for example, an n-type It is formed by doping a P-type impurity (or n-type impurity) on a semiconductor wafer. At least two n-channel MOS transistor groups 21 are provided in the P-type well region in the row direction.

The n-channel MOS transistor group 21 is disposed in a first n ⁺ type-region first silicon gate terminal-second n ⁺ type region-2 silicon gate terminal-3n ⁺ type region and is connected in series to two current paths. And a pair of n-channel MOS transistors having two gate terminals arranged in parallel with each other in the row direction.

The second n ⁺ type region is provided to one drain region of a pair of n-channel MOS transistors, and is simultaneously provided to another source region.

In addition, the P type well region 20 includes three P ⁺ type diffusion regions 22. The P ⁺ type diffusion regions 22 are arranged on both sides of each of the n-channel MOS transistor groups arranged in the row direction.

The intermediate region 30 is a region existing between the plurality of independent well regions arranged in the column direction on the n-type semiconductor wafer (or P-type semiconductor wafer). In the case where the intermediate region 30 is an n-type semiconductor wafer, at least two p-channel MOS transistor groups 31 in the row direction are formed to correspond to at least two n-channel MOS transistor groups 21 in the well region. Equipped.

The P- channel MOS transistor group 31 is first 1p ⁺ type region, the first silicon gate terminal - the 2p ⁺ type region, the second silicon gate terminal - are arranged in the 3p ⁺ type region, the series connection of two current It consists of a pair of P-channel MOS transistors having two gate terminals arranged in parallel with each other in the passage direction.

The second p ⁺ type region is provided to one drain region of a pair of p-channel MOS transistors and is simultaneously provided to another source region.

In addition, the intermediate region 30 includes three n ⁺ type diffusion regions 32. The n ⁺ type diffusion regions 32 are arranged on both sides of each of the above-described p-channel MOS transistor groups arranged in the row direction. In order to prevent the unique latchup phenomenon of the CMOS integrated circuit, the n ⁺ and p ⁺ type diffusion regions 22 and 32 are used to fix the substrate potential of the well region 20 and the intermediate region 30. The basic cell 10 constructed as described above forms a pair of CMOS transistors with corresponding n-channel and p-channel MOS transistor groups 21 and 31 on the same column.

Therefore, one basic cell 10 can form four CMOS inverters, two two input NAND gate circuits, and one four input NAND gate circuit. In addition, the basic cell 10 is used to configure an input / output protection circuit between the bonding pad and the internal logic circuit.

As shown in FIG. 4, a master chip is formed on a master wafer according to the present invention in which a basic cell 10 is formed on a front surface of a wafer in a matrix through a metal wiring process by a multilayer wiring technique. The master chip shown in FIG. 5 is formed on the wafer through multi-layer wiring revolving such as forming contact holes, forming first layer metal wirings, forming vertical path holes, forming second layer metal wirings, and forming bonding pads. The master chip is composed of the internal logic circuit on the basic cell array in the center and the I / O protection circuit using the unused basic cell around the internal tissue circuit, and the bonding pad is formed on the basic cell remaining around the I / O protection circuit. It is configured by. When machining the master chip from the wafer, as shown in FIG. 6, the unused basic cell portion around the forming area of the bonding pad 40 is cut by the scribe line 50, but each basic cell is independently Because it is formed, no electrical disturbances occur.

As described above, in the present invention, an independent basic cell is formed in a matrix form on the front surface of the wafer and the chip size of the application circuit is determined by using a multi-layered wiring method on the basic cells, so that the size of the chip can be optimized and the circuit design can be reduced. Since the gates available for use are not limited, the circuit design is very free. In addition, the supplier only needs to produce and manage the master wafer of the present invention using only one mask, so that each gate array is produced by a predetermined number of gate units as in the prior art, and there is no need to distinguish and manage a product.

The present invention has been described only with respect to the above embodiment, but is not limited to this embodiment. For example, the wiring region may be separately provided in the intermediate region.

Claims (7)

A plurality of first conductive independent well regions 20 arranged in a row direction on the entire surface of the second conductive semiconductor wafer; A plurality of second conductive MOS transistor groups (21) each arranged in a row direction in the first conductivity type well regions, each having current paths connected in series and gate terminals arranged in row direction in parallel with each other; A plurality of first conductivity type diffusion regions 22 disposed on both sides of the second conductivity type MOS transistor group; A second conductive intermediate region 30 formed between adjacent well regions 20 arranged in the longitudinal direction; A plurality of first electrodes arranged in a row direction in the intermediate regions 30 corresponding to the second conductive MOS transistor group, respectively, having current paths connected in series and gate terminals arranged in row directions in parallel with each other; A single conductive MOS transistor group 31; And a plurality of second conductive diffusion regions (32) disposed on both sides of the first conductive MOS transistor group. The method of claim 1, wherein a plurality of master chips are formed through a multilayer wiring process in order of forming contact holes, forming first layer metal wirings, forming vertical path holes, forming second layer metal wirings, and forming bonding padding. Borderless master slice semiconductor device, characterized in that. 2. The basic structure of claim 1, wherein two second and first conductive transistor groups 21 and 31 formed in each of the plurality of first conductive well regions 20 and the intermediate region 30 are one basic. A borderless master slice semiconductor device, comprising forming a cell. 2. The borderless master slice semiconductor device according to claim 1, wherein said at least one first and second conductive transistor group is provided in a configuration of an internal logic circuit of a master chip. The borderless master slice semiconductor device according to claim 1, wherein the at least one first and second conductive transistor group is provided with an input / output protection circuit of a master chip. 6. The method of claim 1, 3, 4 or 5, wherein the second conductive semiconductor wafer and the second conductive intermediate region 30 are n-type semiconductors, and the first conductive well regions. When 20 is formed of a p-type semiconductor, the plurality of second conductive MOS transistor groups 21 are formed of n-channel MOS transistors, and the plurality of first conductive diffusion regions 22 are formed of p ^+. And a twelfth conductive transistor group 31 formed of a p-channel MOS transistor, and the plurality of second conductive diffusion regions 32 are formed of an n ⁺ type semiconductor. Borderless master slice semiconductor device. 6. The method of claim 1, 3, 4 or 5, wherein the second conductive semiconductor wafer and the second conductive intermediate region 30 are p-type semiconductors, and the first conductive well regions When 20 is an n-type semiconductor, the plurality of second conductive MOS transistor groups 21 are formed of p-channel MOS transistors, and the plurality of first conductive diffusion regions 22 are n ⁺ type. The first conductive transistor group 31 is formed of an n-channel MOS transistor, and the plurality of second conductive diffusion regions 32 are formed of a p ⁺ type semiconductor. Less master slice semiconductor device.

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