JPS58221462A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To reduce the number of command lines, by dividing a system command controlling flip flops (FFs) into a master command register for the synchronous command of the whole processors and a slave command register to control individual processor commands. CONSTITUTION:An operation controlling device 1 is provided with a common command generating part to generate commands to the whole processors 21- 2n by an access from the device itself or a debug processor 3. Respective processors 21-2n have command receiving parts to receive the command supplied from the operation controlling device 1 or the debug processor 3 through a common bus. By supplying the command from the operation controlling device 1 or the debug processor 3 to respective processors 21-2n individually or the whole processors 21-2n in common, the function of the operation controlling device 1 is dispersed into respective processors 21-2n and the number of lines to be used exclusively for command transmission is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor system, and particularly to a command control method for each processor in the system.

Generally, in this type of system, multiple processors are connected to a common bus, and operations such as starting and stopping the processors are controlled via individual lines from a common operation control device (also called a subprocessor or service processor). It is done through. Therefore, as the number of processors increases, the number of lines for supplying control commands (I-mantle) such as start and stop to each processor increases, and eventually the number of processors that can be connected to a common path depends on the number of lines. will be restricted.

Therefore, it is desirable to minimize the number of dedicated 2-in for commands so that commands can be supplied to a large number of processors.

FIG. 1 is a block diagram showing a conventional example of a multiprocessor system, and FIG. 2 is a block diagram showing a conventional example of an operation control device. In FIG. 1, 1 is an operation control device that is commonly provided in the system, 21 to 2n are processors, 3 is a debug processor that mainly performs tests, 4i1 is an operator console, and a line for a mantle. That is, the operation control device 1 , the processors 21 to 2n and the debug processor 3 are connected in parallel to each other via a common bus (BUS), and commands from the operation control device 1 are given to each processor 21 to 2n via a dedicated line t.This command line t is 1 for one processor
One command is required for each command, for example START.

Commands that have an exclusive relationship such as STOP are shared on one line. For example, 0" is used to stop,
1# can be used to indicate the start. Nao, Coman)
The 'I command can also be issued from the operator console 4 via the Depak processor 3 and the operating control device 1.

Here, the operation control device will be explained with reference to FIG. 2. Note that the commands are considered to be start and stop commands. Therefore, the command line tF! of FIG. , 5TOP/5TART lines. In FIG. 2, 51 to 5n are processors 21 to 2n K, corresponding command generation units, and 8 Ws.
t is a start command switch, 5WBp is a stop command switch, FFI is a clip-flop for start/stop command control corresponding to the processor 21, O
R1 is an OR gate for a start command, 0R12 is an OR gate for a stop command, AN1 is a data write control gate, and BFI is a command output buffer gate. Note that the configuration of the command generation units 52 to 5n is the same as that of 51.

Hard switches 5w5t, 5w8 in the operation control device 1
The start and stop commands by p are simultaneously supplied to all n processors. For example, a start request made by switches 8W and t is simultaneously input to all start commands OR11 to 0Rnl of the command generation units 51 to 5n, and all 7 lip 70 knobs FFI to FFn are in the start mode υ, command output Buffer gate BFI~B
5TOP/5TART hard line (t) through Fn
In both cases, the start command is supplied to all n processors at the same time.On the other hand, the stop request by the switch S'wsp is sent to one OR12 to 0Rn2 as in the case of a start request. They are input simultaneously, and all flip-flops FFI-FFn are in the stop mode.The stop command is supplied to all processors simultaneously.

On the other hand, commands from the operator console 4 via the debug processor 3 are sent via the common bus BtJ.
7 lip-flop FFI of operation control rack M1 through 8~
By writing predetermined data to all or individually of FFn, commands can be supplied to all or individually of the processors.

In this case, the write addresses to each of the 7 lip-flops are different from each other, and the data write control gates) ANI to A
They can be accessed individually under the control of Nn. The structure of the write data is such that bits at predetermined positions are associated with each other as a start command bit and a stop command bit, and the corresponding bits are activated to become command data. Therefore, the start command bit is OR gate C
The stop command bits correspond to the inputs 11l to 0n1, and the stop command bits correspond to the inputs oui2 to 0Rn20.

In this case, the operations in response to the start command and stop command in the command generation units 51 to 5n are the same as in the case of the command command from the switch 5Wst+8WBp.

According to the conventional method, the number of hard lines for commands from the operation control device increases in proportion to the number of processors connected to the common bus, which limits the number of processors. Since all the generation functions are concentrated in the operation control device, the hardware capacity of the operation control device increases in proportion to the number of processors.

This invention was made in view of the above, and by reducing the number of hard wires for command commands that are supplied to multiple processors connected to a common bus, it eliminates the limit on the number of processors that can be installed, and also The purpose is to reduce the burden on the operation control device by distributing the generation function to each processor.

The feature is that the operation control device that supplies predetermined commands to multiple processors is provided with a common command generation unit that is accessed from the device itself or the debug processor and issues commands to all the processors simultaneously;
Each processor is provided with a command receiving section that receives commands from the operation control device or commands given from the debug processor via a common bus, and commands can be sent from the operation control device or debug processor to each processor individually or to all processors in common. The functions of the operation control device are distributed to each processor, and the number of dedicated lines for sending commands is reduced.

Embodiments of the present invention will be described below with reference to the drawings.

3 to 5 are block diagrams showing embodiments of the present invention, in particular, FIG. 3 shows the overall structure of the multiprocessor, FIG. 4 shows the structure of the operation control device, and FIG. 5 shows the processor. FIG. 6 is a flowchart showing the operation procedure from the debug processor.

This invention utilizes the command line t as shown in FIG.
has been significantly reduced compared to FIG. 1, the configuration of the operation control device has been simplified as shown in FIG. 4, and each processor has a slave command register S as shown in FIG.
It is characterized by the provision of CMR. In addition, the third ~
In FIG. 5, items in the same row as those shown in FIGS. 1 and 2 are designated with the same symbols or numbers. Therefore, the difference is as follows. That is, in FIG. 4, ANll is a stop command priority gate, and MCMR is a flip-flop (master command register) for controlling start/stop commands for all processors.
It is. In FIG. 5, SCMR is a flip 70 block (slave command register) for controlling start/stop commands for each processor, OTIPl is an OR gate for stop commands, 0RP2 is an OR gate for start commands, and AN
Pl is a stop command priority gate, and ANP2 is a data write control gate. When the system is reset, the master command register MCM is configured to stop and the slave command register 8CMR is configured to start.

Here, from inside the operation control device, press switch 8W.
, t, sw, . A case will be described in which a command is given via , t, sw, .

a) Start command command, that is, start by pressing switch 5Wst) Required)
f[i This is the same as in FIG. 2 in that the master command register MC'MR (corresponding to the flip 70 block FF1 in FIG. 2) is in the start mode.

In this case, as is clear from FIG. 4, the command line t' is commonly connected to all processors, so in the start mode, it is set to "1" via the buffer (BFI).
A signal set to K is given to all processors as a start command. In the command receiving section of each processor shown in FIG. 95, the start command is received by OTI (or game) and P2, and under the control of ANPl under the condition that there is no stop command (stop command priority game). ), the start command is taken into the processor.

b) A stop request by operating the stop command command switch 8W6 is sent to the master command register MCMR via OR12.
As a result, MCMR is set to stop mode. Note that a system reset signal is also input to the OR gate 0R12. As in the case of the start command in a) above, the command line t is set to "Om", so the stop command is given to all processors in common.

The command receiving section in Fig. 5 receives the stop command (or game)
When inputting into the processor via ORPI,
The stop command priority gate ANPI is closed to lock the start command from being taken into the processor.

Next, the case where instructions are given from the debug processor will be explained with reference to FIG. 6 as well.

a) Instructions for all processors In this case, write to the master command register MCM of the operation control device shown in FIG.
This is done by writing predetermined data through the . In this case, the game ANI is configured to be opened only when a predetermined address previously assigned to the register MCMR is given. The format of the data is such that bits at predetermined positions are allocated in advance as start bits or stop bits, and the corresponding bits are activated to become command designation data. In this way, master command register MC? VIR enters the start mode or stop mode as shown in FIG. 6(A) or (B), but the subsequent operation is the same as in the case of a start or stop command using a switch.

The data for the stop command is input to the register MCMR via the stop command priority game) ANll, so even if the start bit is set, it will be ignored and the stop mode will be set.The stop command has priority. be done.

b) Instructions to individual processors In this case, instructions are given by writing predetermined data to the slave command register 8CMR in each processor as shown in FIG. 6(C), (D) or (E). Here each register S
The address for write access to the CMR is set to be different for each processor, and the data write control game (ANP) is executed only when a predetermined address is received.
Make sure to open 2. Note that the format of the write data is the same as when giving commands to all processors. Also, register f! IIcMR is given a start command.

In addition to preparing bits corresponding to stop commands, etc., the system is configured to enter the start mode upon system reset. In this case, the stop bit is set in register SCMR and
When a stop command is input to the processor via l, the stop command priority game) ANPl locks the input of the start command to the processor, and when the start bit is set in register 8CMR. , the start command via the OR gate ORP2 is read as electrical, indicating that there is no stop command, as in the case of a switch operation.

As described above, according to the present invention, the flip-flops for system command control, which were concentrated in the conventional operation control device, are divided into a master command register for simultaneous commands of all processors and a slave command register for controlling individual processor commands. Since the cono slave command register is shared among each processor, (1) the number of lines for command commands can be reduced, which enables multiprocessing with more processors than before.

(2) The burden of system command control operations on the operation control device can be reduced.

The following effects can be obtained.

Note that although the explanation has been mainly given to start and stop commands above, the same can be applied to other commands as well.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional example of a multiprocessor system, FIG. 2 is a block diagram showing the configuration of the operation control device in FIG. 1, FIG. 3 is a system configuration diagram showing an embodiment of the present invention, and FIG. 5 is a block diagram showing an operation control device according to the present invention, FIG. 5 is a block diagram showing a command receiving section on the processor side according to the present invention, and FIG. 6 is a flowchart explaining the operation procedure from the debug processor. Code explanation 1... Operation control device, 21-2n...
Processor, 3... Debug processor, 4.
...Operator console, 51~5n...
...Command generation section, t, t...Command twin, 5Vv8t...Switch for start command, 5WF1p...Switch for stop command, FF1... ...Flip-flop, MCMR,
...Master command register, SCMR...
...Slave command register, 0RII, 0R
12t 0RP1 *OR, P2...OR gate, ANI, ANll, ANPt. ANP2... Ant game), BFI...
・Buffer gate (A) (C) Figure 6 CB) + [)) (E)

Claims (1)

[Claims] A plurality of processors and a predetermined control command (
In a multiprocessor system in which an operation control device that provides commands) and a debug processor that monitors and tests the processor and supplies predetermined commands are connected in parallel to each other via a common bus, the operation control device has A common command generating section is provided that is accessed from the device itself or the debug processor and issues a common command to all the processors, while each processor receives a common command given via the operation control device. an individual command receiving section for receiving individual commands given via the debug processor, and selection means for selecting either the common command or the individual command; A multiprocessor system characterized in that each processor is controlled by individual commands.