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JPS58182441U - semiconductor integrated circuit - Google Patents

semiconductor integrated circuit

Info

Publication number
JPS58182441U
JPS58182441U JP1982079348U JP7934882U JPS58182441U JP S58182441 U JPS58182441 U JP S58182441U JP 1982079348 U JP1982079348 U JP 1982079348U JP 7934882 U JP7934882 U JP 7934882U JP S58182441 U JPS58182441 U JP S58182441U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit
resistor
semiconductor integrated
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982079348U
Other languages
Japanese (ja)
Inventor
岩崎　楠也
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP1982079348U priority Critical patent/JPS58182441U/en
Publication of JPS58182441U publication Critical patent/JPS58182441U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のサージ対策を施した回路図、第２図はそ
の具体的な内部構成を示す断面図、第３図は絶縁破壊状
態を示す拡大上面図、第４図は来者案巣積回路の要部の
拡大上面図、第５図は本考案の他の実施例を示す拡大上
面図であって、５は抵抗体、１２はコンタクト、１３は
絶縁破壊痕、１４は電源共ラド、を夫々示している。Figure 1 is a circuit diagram of a conventional surge countermeasure, Figure 2 is a cross-sectional view showing its specific internal configuration, Figure 3 is an enlarged top view showing dielectric breakdown, and Figure 4 is a visitor guide. FIG. 5 is an enlarged top view showing another embodiment of the present invention, in which 5 is a resistor, 12 is a contact, 13 is a dielectric breakdown trace, and 14 is a power supply Radar. , respectively.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 外部回路に直結される入力パッドと内部回路との間に半
導体基板に逆導電型の不純物を導入して形成した抵抗体
を挿入すると同時に該抵抗体と基板との間にダイオード
を形成して外部回路からのサージに対する保護をはかっ
た半導体集積回路に於て、上記人力パッドと上記抵抗体
とのコンタクト箇所を該集積回路へ電源を供給する電源
パッドと離隔した位置に設けて成る半導体集積回路。A resistor formed by introducing impurities of the opposite conductivity type into a semiconductor substrate is inserted between the input pad directly connected to the external circuit and the internal circuit, and at the same time a diode is formed between the resistor and the substrate to connect the external circuit. In a semiconductor integrated circuit designed to protect against surges from the circuit, a contact point between the human power pad and the resistor is provided at a position separated from a power supply pad that supplies power to the integrated circuit.
JP1982079348U 1982-05-28 1982-05-28 semiconductor integrated circuit Pending JPS58182441U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982079348U JPS58182441U (en) 1982-05-28 1982-05-28 semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982079348U JPS58182441U (en) 1982-05-28 1982-05-28 semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS58182441U true JPS58182441U (en) 1983-12-05

Family

ID=30088533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982079348U Pending JPS58182441U (en) 1982-05-28 1982-05-28 semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS58182441U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52102689A (en) * 1976-02-24 1977-08-29 Philips Nv Semiconductor device having safety circuit
JPS52123182A (en) * 1976-04-09 1977-10-17 Fujitsu Ltd Input and output end protection system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52102689A (en) * 1976-02-24 1977-08-29 Philips Nv Semiconductor device having safety circuit
JPS52123182A (en) * 1976-04-09 1977-10-17 Fujitsu Ltd Input and output end protection system

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