JPS58125290A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a highly integrated semiconductor storage device which operates stably at a high speed by arraying a clamping diode at each boundary part between a column line driving circuit and a memory cell which uses a normally off type and a normally on type Schottky FET. CONSTITUTION:When the level at a terminal 708 of the column line driving circuit 705 rises, the normally on type Schottky FET709 is turned on and the FET710 is turned off through an inverter to select a corresponding column line 701 of a memory cell array 700. Then, a static memory cell using a normally off type Schottky FET which uses the column line 701 in common is selected. In this case, the clamping diode is arrayed at the boundary part between the driving circuit and memory cell and the potential at the column line 701 having started rising in level is clamped to a prescribed low level in a short time, so that a constant current flows to the ground through the FET709 and diode 706, but does not flow to the column line 701. Consequently, the rising is speeded up and potentials at respective parts of the column line 701 are made constant to obtain the semiconductor storage device which is integrated to a high degree and operates stably at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device using a Schottky-cate field effect transistor (hereinafter abbreviated as Schottky FET).

In recent years, three-terminal active devices that exceed the operating speed of bipolar transistors include G, A, and crystal M E 8.
(Metal 8emiconductor) ・F
ET attracted attention, and these FETs were integrated and
G.A. Integrated circuits are being actively prototyped.

The present invention provides a normally-on type Schottky FE in a memory cell.
Tt- and normally-on type Schottky FBTs are used in the peripheral circuits to efficiently supply high-speed signals generated in the peripheral circuits to the cell array.

A circuit using a normally-on Schottky FET and a circuit using a normally-off Schottky FET have different power supply voltages and signal amplitudes, and when they are integrated on the same substrate, they cannot be directly coupled. Furthermore, when driving a large-area cell array, it is necessary to suppress the potential difference between the two ends of the cell as much as possible. According to the present invention, a semiconductor memory device can be obtained in which the potential difference within the array is suppressed as much as possible by directly connecting the two transistors using a level clamp diode and specifying the position where the diode is added.

In a semiconductor memory, memory cells are arranged in a matrix, and around them are arranged circuits for selecting cells, circuits for driving selected cells, circuits for amplifying read signals from the cells, and the like. FIG. 1 shows a schematic diagram of a semiconductor memory.

This figure shows the arrangement of each circuit in a chip of a semiconductor memory integrated circuit device.
is a cell array in which memory cells are arranged in a matrix,
101 is a signal conversion circuit that converts a signal for selecting the column direction of the cell array 100 supplied from the outside into a chip internal signal; A column selection circuit 103 selects the column selection circuit 120, and a drive circuit 103 drives the memory cells connected in the column direction selected by the column selection circuit 120. In addition, in the explanation, the circle mark shown in the cell array 100, for example 108, means a memory cell,
A line in the column direction, for example 109, is a column line for sending a drive signal from the drive circuit 103 to a selected cell. When a cell drive signal is applied to a selected column line, signals are read out from all memory cells connected to that column line and supplied to the signal amplification circuit 104 through a row line such as 110 in the row direction. be done. The read signal amplified by the signal amplifier 104 is selected by the row selection circuit 105, and only the read signal corresponding to one row line is sent to the output buffer 107.
It is designed to be output outside the chip through. Further, 106 is a signal conversion circuit that converts a signal for selecting the row direction of the cell array supplied from the outside into a chip internal signal, and its output is supplied to the row selection circuit 105. The above is a simple explanation of the read operation, but for the write operation, the column line and row line selection operations are the same, and the write information is supplied only to the row line that was left behind, and the information is transferred to the memory cell. It is now written.

Note that the signal conversion circuit 106 also includes a circuit that generates a write signal and a pledge information signal inside the chip in response to a signal supplied from outside the chip.

The read and write operations of semiconductor memory have been briefly described above, but it is important to integrate a large number of memory cells on a chip, and it is necessary to minimize the area occupied by a circuit as simple as possible. be. for that purpose,
It is effective to use a normally-off Schottky FET, which does not require a level shift circuit and has a simple circuit configuration. On the other hand, the circuit that drives the large number of memory cells connected to each column line drives the large load capacitance attached to the column line, so even if the circuit becomes somewhat complex, it requires an element that can flow a large current. Yes, normally-on Schottky FET
It is effective to use FIG. 2 shows a sectional view of a normally-off Schottky FET, and FIG. 3 shows a sectional view of a normally-on Schottky FET. 200 in Figure 2
G and A are semi-insulating substrates, 201 is a heavily doped N-type ion-implanted layer for the source and drain portions, and 202 is a low-concentration N-type ion-implanted layer for the channel forming portion. Reference numeral 203 denotes a Schottky gate electrode, which is formed with a metal group (for example, At) to form a Schottky contact with the N-type ion implantation layer 202. 204 is a drain electrode, 20
Reference numeral 5 denotes a source electrode, both of which are patterned with a metal group (eg, Au-Ge alloy, etc.) that makes resistive contact with the N-type ion implantation layer 201. In this type of device, a depletion layer 206 extending under the gate electrode expands and contracts up and down depending on the gate voltage, thereby forming a drain.

FET operation is performed by changing the current flowing between the sources. Since the device shown in Fig. 2 is a normally-off Schottky FET, when the gate voltage is zero, the depletion layer 2
06 reaches the lower end of the channel forming part 202, and the drain
No current flows between the sources. The gate voltage at which current begins to flow between the drain and source is called the threshold voltage VT, and in the case of a normally-off Schottky FET, this value is approximately 0, IV. When the gate voltage is a positive voltage equal to or higher than the threshold voltage Vt, the depletion layer 206 contracts, and current flows between the drain and source. - 3000G, A
, semi-insulating substrate, 301 high concentration N-type ion implantation layer, 3
The gate electrode 03, the drain electrode 304, and the source electrode 305 are the same as those of the normally-off Schottky FET, but the thickness of the low concentration N-type ion implantation layer 302 is thicker than that of the normally-off Schottky FET.

Therefore, even when the gate voltage is zero, a current flows between the drain and the source, and the gate voltage becomes a negative voltage, which causes the current to stop flowing due to V. The threshold voltage Vt of a normally-on Schottky FET is usually -1.0~
-zO■ value is used. Normally-off type and normally-on type F with the same element dimensions and the same gate voltage
Comparing the drain-north currents of the ETs, the latter allows several times larger current to flow.

Figure 4 shows an example of a memory cell circuit conveniently used in a normally-off Schottky FET'.
In this case, the circuit can be constructed by directly connecting FETs without requiring a level shift circuit, and the circuit can be constructed with a small number of elements. In FIG. 4, 400 is a word line, 401, 40
2 is a data line. The ninth column line explained in FIG. 1 corresponds to the word line 400 in this figure, and the row line corresponds to the data lines 401 and 4.
Corresponds to 02. In Figure 1, one row line is displayed for each cell, but in reality, there are one row line as shown in Figure 4.
A pair constitutes a data line. 403°404 is resistance,
405, 406, 407, and 408 are normally-off Schottky FETs. The sources of FETs 406 and 407 are commonly grounded, and the drains are connected to the resistors 403 and 40, respectively.
4 to the power supply Vc (for example, +〇, 5 V), and the gates are connected to opposite nodes 410 and 409, respectively.
are connected to form a flip-flop circuit. Finally, the drains of FETs 405 and 408 are connected to data lines 401 and 402, respectively, the sources are connected to nodes 409 and 410, respectively, and the gates are connected to word a 400. Here, each resistance value etc. is selected so that one of the FETs 406 and 407 is in the on state and the other is in the off state, and the FET 406 is in the yi-y, FET
B'l'407 is off, and FET406 is off.
:y, binary information “0°” corresponding to two cases where FET 407 is on.

"l" is stored. When a drive signal is applied to the word line 400, the FETs 405 and 408 are turned on, and the storage signal is read out to the data line. The pledging operation is performed by applying a drive signal to word @1400 and FET405.40.
This is done by lowering the potential of either the data line or 401 or 402 after turning g to yK. The amplitude of the word line signal for driving a memory cell using such a normally-off WFET is limited by the threshold voltage Vt of the FET and the forward characteristics of the Schottky gate, and is approximately 0.6
That's about it. This restriction will be explained in more detail below.

Suppose that the FET 406 is on, the FET 405 is off, and information "0#" is stored in the cell. At this time, the node 409 is approximately at ground potential, -10,000, and the node 410 is approximately 0.
, 5 to 0.6 ■. When a cell is unselected,
Since the node 4091410 needs to be electrically isolated from the data lines 401 and 402, the FETs 405 and 408t must be turned off.

Therefore, it is necessary to maintain the voltage of word @400 at the potential of node 409, that is, the ground potential 4[. Next, when the cell is in a selected state and a read operation is performed, the potential of the word line 400 rises and the FETs 405 and 408 are turned on, but the word line voltage cannot be increased indefinitely.

The reason is that in nine FETs using Schottky Kate,
Since the gate electrode, source electrode, and drain electrode constitute a Schottky diode, when the gate voltage is approximately 0.6 V higher than the source or drain voltage, current flows from the gate to the source or drain/electrode. Because it begins. Consider this situation using the cell in Figure 51!4.

Now, if information "01" is stored in the cell, the node 409 is almost at ground potential, so the word line 409
When the potential of the word line 400 reaches approximately 0.6■, a current begins to flow from the word edge 400 to the node 409, and further to the word line 4.
When the potential of node 00 rises, the potential of node 409 begins to rise, and eventually nodes 409 and 410 become the same potential, causing information destruction. Furthermore, a phenomenon similar to that during reading may occur during writing as well. Therefore, when the cell is in a non-selected state, in order to maintain the stored information in the cell and not destroy the stored information during reading and writing, the signal amplitude of word g4oo must be kept to about 0.6 V. I understand that.

Next, the word line drive circuit will be described. As mentioned above, it is efficient to use a normally-on Schottky FET in this drive circuit, and an example thereof is shown in FIG. The same figure (→ is 5DFL (Schottky
Logic). In the figure, 500 is an input terminal, 501 is an output terminal, 502, 503 are diodes, 504, 505
．． 506 is a normally-on Schottky FET,
FET504 is a level shift circuit, FET505,5
06 is for controlling the output potential. The anode of the diode 502 is connected to the input terminal 500, the anode of the diode 503 is connected to the cathode of the diode 5020, the drain of the FET 504 is connected to the cathode of the diode 5020, and the gate and source of the FET 504 are commonly connected to the power supply It constitutes a shift circuit. Furthermore, the cathode of the diode 503 is FET5
The drain of FET506 is connected to the gate of FET506, and the drain of FET506 is connected to the gate of FET506.
It is commonly connected to the source and gate of the ET 505, and is also connected to the output terminal 501. The drain of FET 505 is connected to power supply VD, and the source of FET 506 is grounded. As described above, compared to a circuit using a normally-off Schottky FET, this circuit requires an extra level shift circuit, and the circuit configuration is accordingly more complicated. Note that Vo in this circuit is 2V,
V is -1.5V, normally-on Schottky FET (
7) As the L threshold voltage Vr, -1V is generally used.

Since the output of this circuit changes from about the ground potential to the potential of VD, the signal amplitude is also about 2V. Input terminal 5
A signal of the same potential as the output terminal 501 is input to the terminal 00, and the voltage level is lowered by about 1.2 V by the diodes 502 and 503. Therefore, the input signal is "L".

The FET 506 turns off and on in response to "H", and the output potential also changes from "H" (2V) to "L" (approximately 0V).

In this case, the way the input signal and output signal change are exactly opposite. In addition, in the circuit of FIG. 5(a), the FET
Even if 504 is replaced with a resistor, the operation is basically the same. The circuit shown in FIG. 5(b) is a push-pull version of the circuit shown in FIG. 5(a) in order to further reduce the current consumption. The input terminal is 51o1, the output terminal is 511, and 512 is an inverter for inverting the input signal. Diode 513゜514.515,516, FET517,5
The operation of 18 is the same as in the case of ((translation), but F
Since only one of ET519 and 520 is always on, it is suitable for low power consumption. Note that in the circuit of (b), the wiring is such that the direction of change in input and output is the same direction. However, since the output amplitude of the circuit (a) is approximately 2V and the output amplitude of the circuit (b) is approximately 1.5V, it is not possible to directly connect the memory cells mentioned above and these peripheral circuits. Some kind of ingenuity will be needed. Figure 6 shows
A level clamp diode 706k (11 people) is installed at the boundary between the cell array 7oo and the column line drive circuit 705. With this circuit configuration, the drive circuit 70
The output level of 5 is the signal voltage 0 allowed by the memory cell.
．． Since the output waveform is clamped at 6V and at the same time within a range where the rising edge of the output waveform is fast, a high-speed signal can be supplied to the selected column line. Furthermore, by using a clamping diode at the boundary between the cell array and the drive circuit, the near and far ends of the column line, for example column line 701, can be
The potentials at the time of selection of 711 and 707 can be kept constant, allowing constant operation of the memory cell. Now column @701
When FET 708 is in the selected state, the potential of column line 708 becomes "H" level, FET 709 is turned on and FET 710 is turned off, the on/off relationship of these FETs is reversed, and the potential of column line 701 begins to rise. Then, as mentioned earlier, when the voltage reaches about 0.6 V, the diode 706 is activated and the waveform is clamped. At this time, FET709
A steady current flows from the diode 706° to ground, but
The diode 706 is connected to the cell array 700 and the driving circuit 70.
5, this steady current can flow without passing through the column line 701. the result,
At the time of selection, the potential can be kept constant at the near end and far end of the column line, allowing stable operation of the memory cell.

As mentioned above, normally-off Schottky FET
t- used for static type memory cells, and further used normally-on type Schottky FET t- for column line drive circuits,
By adopting a circuit configuration in which a clamping diode is placed at the boundary between the two, it is possible to realize a semiconductor memory device that is highly integrated, high-speed, and capable of stable operation.

FIG. 7 shows signal waveforms in the circuit of FIG. 6. (a) shows the signal waveform input to the terminal 708. When the column line 701 is selected, the signal level rises from approximately OV to 2V, and as a result, the potential of the column line begins to rise. . (b) shows this situation, where the solid line is the waveform in the circuit diagram of FIG. 6, and the broken line is the waveform when the clamping diode 706 is not provided. As can be seen from this waveform, the amplitude of the column line is suppressed within the permissible signal amplitude of the memory cell, and the rise 9 of the output signal of the drive circuit is also fast. Although the falling part of the line II has not been described, in the drive circuit shown in Fig. 5,
If the fall time is 9 hours, the rise time and the rise time are also quite short.
The rise time is not an issue.

Although one embodiment of the present invention has been described above, the present invention is not limited to memory devices using compound semiconductors G and A.
It is also effective in 9Sr memory devices using Schottky gate type FETs. In addition, substrates other than semi-insulating NaAs substrates, such as G, A,
Alternatively, it may be an SL semiconductor memory device, or even an SL semiconductor memory device using an O3 m crystal. Further, in the circuit shown in FIG. 5, the level shift circuit is constructed of diodes and FETs, but the level shift circuit may have other circuit constructions.

The ninth example is the diode and FE as shown in Figure 8(a).
A device using a level shift circuit consisting of T% and capacitance is preferable for use in the present invention. Note that the operation is essentially the same even in a circuit in which the FET 804 in FIG. 8(a) is replaced with a resistor. In the figure, a capacitor 803 operates as a coupling capacitor, and is added to rapidly discharge the potential of the node 808 when the input signal 800 falls at 9:00.

In addition, diodes 801, 802 . FET8U4 is provided to fix the potential of node 808 to a constant value when the input signal is in a steady state. Further, when the input signal rises, the potential of the node 808 changes rapidly to the High level due to both the transient current flowing through the capacitor 1i803t and the direct current flowing through the diodes 801 and 802.

In this circuit, the DC current in the level shift section can be reduced, so compared to the 5DFL circuit shown in FIG. 5(a),
It can be said that it is suitable for low power consumption and driving high loads.

The circuit of FIG. 8(b) has a push-pull configuration using the circuit of FIG. 8(a) as a basic circuit, and the input/output signal levels and circuit operations of each part are as follows except for the level shift section. This is the same as the case in FIG. 5(b).

This circuit can be used as is as the column line drive circuit 705 in FIG. 6, and can achieve lower power consumption and higher speed operation than the circuit shown in FIG. 5(b). In addition, in FIG. 8, FET804.805,
806, 815, 817, 81ti.

Of course, 821, 823, and 824 are normally-on Schottky FETs.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the arrangement of circuits within a chip in a semiconductor memory device, and FIGS. 2 and 3 are U, A,
4 is a cross-sectional view showing the structure of a shot gate type field effect transistor, FIG. 4 is a circuit diagram showing an example of a memory cell used in the present invention, and FIGS. 6 is a circuit diagram showing an example of a memory cell driving circuit used, FIG. 6 is a circuit diagram showing a main part of an embodiment of the present invention, FIG. 7 is a diagram showing signal waveforms in the circuit of FIG. 6, and FIG. FIGS. 8(a) and 8(b) are circuit diagrams showing other examples of the memory cell left drive circuit used in the present invention. 400...word a (column line), 401.402...
Data line (row line), 405, 406, 407.408・
・・Normalion type Schottky・K) a F E
T%502.503,513,514,515,5
16°801.802,812,813,818.81
9...Diode, 504,505.54)6,51
7゜518.519,520,804,805,806
゜815.816,821,823.824... Normally-on Schottky gate WFBT, 512...
・Inverter, 706... Level clamp diode, 814.820... Capacity. 1 Figure 02 Vi2 Figure v13 口578 'tE41￥] Figure 7 -579- y 8 Figure T's (b) Continued from page 1 0 Inventor Masahiro Hirayama 3-9-11 Midoricho, Musashino City Nippon Telegraph Musashino Telecommunications Research Institute, Telephone Public Corporation 0 Inventor Masayuki Ino 3-9-11 Midoricho, Musashino City Musashino Telecommunications Research Institute, Nippon Telegraph and Telephone Public Corporation Applicant Nippon Telegraph and Telephone Public Corporation 580-

Claims (1)

[Scope of Claims] 1. A memory cell array in which static memory cells using normally-off Schottky gate field effect transistors are arranged in a matrix, and memory cells arranged in each column of the cell array have common features. A semiconductor memory comprising connected word lines and a plurality of drive circuits that supply drive signals to the word lines using normally-on Schottky-Cate type transistors. Device. 2. The semiconductor memory device according to claim 1, further comprising a level clamp diode provided at each boundary between the plurality of word lines and the plurality of drive circuits.