JPH03192595A - Memory cell and memory integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the contents of a memory from being inverted, to obtain a memory cell with a small area and to make an integrated circuit using the memory cells compact while securing a sufficiently wide noise margin by specifically connecting an FF to two FETs. CONSTITUTION:Since a 1st output 2 of the FF1 is not connected to the source or gate of the 1st FET 4 but is connected to the gate terminal of the FET 4, the charge of a bit line does not flow into the FF1 and influence such as the inversion of data can be prevented. The memory integrated circuit constituted of arranging plural memory cells can secure a sufficiently wide noise margin and extracts an output without using a sense amplifier or the like because the amplitude of a bit line can be changed from the potential of a 1st power supply 65 up to the potential close to that of a 2nd power supply 66. Since only one reading bit line is used, the layout of the circuit can be made compact.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory cell and a memory integrated circuit using the same.

(Prior Art) A memory cell used in a conventional memory integrated circuit is shown in FIG. In FIG. 7, 9 flip-flops, 1
0.11 is a transistor that connects the flip-flop 9 and the first and second read bit lines 14 and 15, respectively, during reading, and 12.13 is a transistor that connects the flip-flop 9 and the first and second write bit lines, respectively, during writing. bit line 17. is transistor, 16 is a read word line, 17.18 is a write bit line, 19
represents a write word line. As shown in the figure, a memory cell is composed of a flip-flop section that stores data and a plurality of transistors that function as switches when writing and reading data. FIG. 8 shows an example in which these memory cells are connected and used as a memory integrated circuit. In FIG. 8, 20 to 22 are flip-flops;
23 to 34 are transistors, 35 is a first read bit line, 36 is a second read bit line, 37 to 39
denotes a read word line, 40 a first write bit line, 41 a second write bit line, and 42 to 44 write word lines. An example of a memory cell flip-flop is shown in FIG. In Figure 9, 45.46
is a depletion type (D type) FET, 47.48 is an enhancement type (E type) FET, 49 is the first power supply,
50 represents a second power supply, 51 represents a first output, and 52 represents a second output. FIG. 10 similarly shows an example of a flip-flop of a memory cell. In this example, transistors 12, 13 for writing or reading are also shown. Figure 9, 1st
In the figures other than Figure 0, the symbol of a D-type FET is used as a transistor, but it does not necessarily have to be a D-type FET.

(Problem to be Solved by the Invention) As shown in FIG. 8, the bit lines of each memory cell are connected through the same contact point. Therefore, when reading from the memory, the contents of the memory may be reversed. This is because when reading data from a memory cell, charges held by bit lines connected via transistors flow into the flip-flop and affect the data in the flip-flop. For example, there is a case where the data of the memory cell read immediately before on the same bit line is an inverted signal with respect to the data of the memory cell read this time.

In this case, the output of the flip-flop, which should hold a high potential, decreases because current flows into the bit line, and conversely, the output of the flip-flop, which should hold a low potential, decreases because current flows from the bit line. rise for. As shown in FIG. 9, the first output 51 and second output 52 of the flip-flop used here are also input to the gate terminals of transistors 47 and 48, so the flip-flop is unstable. You may fall into a situation. And in the worst case where multiple word lines are selected,
It is known that data inversion may occur.

Further, in the conventional configuration, two bit lines were required for reading each memory cell. This is a restriction on the layout design of the memory cell, and also causes an increase in the cell area.

An object of the present invention is to provide a memory cell in which the contents of the memory are not inverted and has a small cell area, and a memory integrated circuit using the same.

(Means for Solving the Problems) A memory cell of the present invention includes a flip-flop, a first field effect transistor having a first output of the flip-flop connected to a gate terminal, and a read word line connected to the gate terminal. a second field effect transistor connected;
The drain terminal of the first transistor and the source terminal of the second transistor are connected, the source terminal of the first transistor is used as a second output, and the drain terminal of the second transistor is used as a first output. do. Further, the memory integrated circuit of the present invention uses this memory cell, connects the first output of this memory cell to a second power supply, connects the second output of this memory cell to a resistor, and connects the other end of this memory cell to a second power source. is connected to a first power supply, or a second output of the memory cell is connected to a second power supply, the first output of the memory cell is connected to a resistor, and the other end of the resistor is connected to a second power supply. It is characterized by being connected to one power source.

(Example) This will be explained using figures. FIG. 1 shows an embodiment of a memory cell of the present invention. In FIG. 1, 1 is a flip-flop;
2 is the first output of the flip-flop, 3 is the second output of the flip-flop, and 4 is the first field-effect transistor (
5 is a second field effect transistor (GaAs MESFET), 6 is a first output of the memory cell, 7 is a second output of the memory cell, and 8 is a read word line. Regarding writing, this example is the first
Since it is the same as Figure 0, it is omitted in the figure. The first output of the flip-flop is connected to the gate terminal rather than the source or drain of the transistor 4, and since the charge of the bit line does not flow into the flip-flop 1, there is no influence such as data inversion. FIG. 2 shows a circuit diagram when a memory integrated circuit is constructed by arranging a plurality of the memory cells. The writing circuit is omitted as in FIG. 1. In FIG. 2, 53 to 55 are flip-flops;
56-58 are first transistors, 59-61 are second transistors, 62-64 are read word lines, 65
is the first power supply (VDD), 66 is the second power supply (V3s)
, 67 represents a resistor, and 68 represents a bit output. Now, let us consider the case where data from the flip-flop 53 is read. Before the read word line 62 is set to High level (H), the voltage of the bit output 68 is the potential VDD of the power supply 65. When the word line 68 goes high, the transistor 59 turns on. When the first output 2 of the flip-flop is H, the transistor 56 is turned on and conduction occurs between the power supplies 65 and 66, so that the bit output 68 becomes Low (L). The potential at this time is a value obtained by dividing VDD by the on-resistance of the resistor 67 and the transistor 65.59, but since the on-resistance can be made sufficiently small, it can be lowered to the vicinity of VSS. Therefore, a sufficient noise margin can be secured, and it is also possible to extract the output without using a sense amplifier or the like.

Figure 3 shows a case where the bit output connections are changed.

In FIG. 3, 69 to 71 are flip-flops, 72
-74 are first transistors, 75-77 are second transistors, 78-80 are read word lines, 81 is a first power supply (VDD), 82 is a second power supply (VSS), 8
3 represents a resistor, and 84 represents a bit output. Contrary to FIG. 2, the first output 6 of the memory cell is connected to the first power supply (VDD) 81.
and connect the second output of the memory cell to the second power supply (VS
S) Connect to 82. The writing circuit is the same as in the example of FIG. 2, but is omitted from the diagram. The operation of this memory integrated circuit is almost the same as the example shown in FIG. 2, except that the directions of the currents flowing through the first and second transistors 72-77 are reversed.

FIG. 4 is a circuit diagram showing an embodiment of the memory cell of the present invention, using the write circuit shown in FIG. 9.

In FIG. 4, 85 is a flip-flop, 86 to 89
are the first to fourth transistors, 90 is the first output of the memory cell, 91 is the second output of the memory cell, 92
93 represents a first write bit line, 94 represents a second write bit line, and 95 represents a write word line. FIG. 5 shows an example in which a plurality of memory cells are arranged to form a memory integrated circuit. In FIG. 5, 96 to 98 are flip-flops, 99 to 110 are transistors, 111 to 113 are read word lines, and 11
4 is a first write bit line, 115 is a second write bit line, 116 to 118 are write word lines,
119 represents a first power supply, 120 a second power supply, 121 a resistor, and 122 a bit output. Reading is almost the same as the example in FIG.

FIG. 6 shows a case where the bit output connections are changed.

Reading is almost the same as the example shown in FIG. In FIG. 6, 123-125 are flip-flops, 126-13
7 is a transistor, 138 to 140 are read word lines, 141 is a first write bit line, 142 is a second write bit line, 143 to 145 are write word lines, 146 is a first power supply, 147 is the second power supply, 1
48 represents a resistor, and 149 represents a bit output. 67, 83
．． 121. The resistor 148 may be replaced with a transistor or the like. This is the resistor 67, 83.121 in Figure 2.3.5.
But it's the same.

In the embodiment described above, the transistor is a D-type GaA
Although sMESFET was used, an E-type may also be used. Also HEMT
etc. can also be used.

(Effects of the Invention) As shown in FIG. 1, the first transistor 4 connects the output of the flip-flop 1 to the gate terminal, so the output of the flip-flop is connected to the output of the flip-flop during reading like a conventional memory cell. There is no risk of flip-flop reversal.

Furthermore, in the present invention, since the amplitude of the bit line can be changed from the potential of the first power supply to the potential near the second power supply, a sufficient noise margin can be ensured, and this can be used for devices with large variations such as compound devices. It can also be applied to Furthermore, since the present invention requires only one bit line for reading, there is an advantage that the layout can be made compact.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the basic configuration of a memory cell according to the present invention, FIGS. 2 and 3 are circuit diagrams showing an example of a memory integrated circuit using the memory cell according to the present invention, and FIG. 4 is a circuit diagram showing a memory cell according to the present invention. 5 and 6 are circuit diagrams showing an example of a memory cell, FIGS. 5 and 6 are circuit diagrams showing an example of a memory integrated circuit using the memory cell of FIG. 4, FIG. 7 is a circuit diagram showing a conventional memory cell, and FIG. 8 is a circuit diagram showing an example of a memory cell. Figure 9 is a circuit diagram showing an example of a memory integrated circuit using conventional memory cells.
1 and 10 are circuit diagrams showing examples of flip-flops used in memory cells.

Claims (2)

[Claims] (1) It has a flip-flop, a first field-effect transistor in which the first output of the flip-flop is connected to the gate terminal, and a second field-effect transistor in which the read word line is connected to the gate terminal; The drain terminal of one transistor is connected to the source terminal of a second transistor, the source terminal of the first transistor is used as a second output, and the drain terminal of the second transistor is used as a first output. memory cells. (2) The first output of the memory cell according to claim 1 is connected to a second power source, the second output of this memory cell is connected to a resistor, and the other end of this resistor is connected to the first power source. or connecting a second output of the memory cell to a second power supply;
A memory integrated circuit characterized in that the first output of the memory cell is connected to one end of a resistor, and the other end of the resistor is connected to a first power source.