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JPS57198632A - Fine pattern formation - Google Patents

Fine pattern formation

Info

Publication number
JPS57198632A
JPS57198632A JP8348481A JP8348481A JPS57198632A JP S57198632 A JPS57198632 A JP S57198632A JP 8348481 A JP8348481 A JP 8348481A JP 8348481 A JP8348481 A JP 8348481A JP S57198632 A JPS57198632 A JP S57198632A
Authority
JP
Japan
Prior art keywords
resist
film
resolution
reflection factor
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8348481A
Other languages
Japanese (ja)
Inventor
Iwao Tokawa
Masaki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8348481A priority Critical patent/JPS57198632A/en
Publication of JPS57198632A publication Critical patent/JPS57198632A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To contrive the improvement of the resolution of a resist pattern by forming an Mo film with low reflection factor under a resist film. CONSTITUTION:An Si alloy layer 2 of 1.2% Al and an Mo film 3 are stacked by evaporation on an Si substrate 1 completed element formation. With a resist pattern 5 made by applying resist 4 for exposure development, the Al alloy layer 2 with high reflection factor is covered by the Mo film 3 with low reflection factor. Therefore, resolution is improved and no residual whiskered resist exists. Next, the Mo 3 is etched by CF4+O2 by using the pattern 5 as a mask. Then, an Mo film is faithfully processed on the mask. Then, after etching the layer 2, plasma incineration is applied to the resist 4 and wiring 2 is completed by applying the removal of etching to the Mo 3 with CF4+O2. In this composition, the resolution of the resist pattern 5 is remarkably improved and fine processing can be done.
JP8348481A 1981-05-30 1981-05-30 Fine pattern formation Pending JPS57198632A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8348481A JPS57198632A (en) 1981-05-30 1981-05-30 Fine pattern formation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8348481A JPS57198632A (en) 1981-05-30 1981-05-30 Fine pattern formation

Publications (1)

Publication Number Publication Date
JPS57198632A true JPS57198632A (en) 1982-12-06

Family

ID=13803741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8348481A Pending JPS57198632A (en) 1981-05-30 1981-05-30 Fine pattern formation

Country Status (1)

Country Link
JP (1) JPS57198632A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6031229A (en) * 1983-08-01 1985-02-18 Tokyo Denshi Kagaku Kabushiki Selective etching method of metal film
JPS61214524A (en) * 1985-03-18 1986-09-24 エヌ・ベー・フイリツプス・フルーイランペンフアブリケン Manufacture of semiconductor
US5066611A (en) * 1990-08-31 1991-11-19 Micron Technology, Inc. Method for improving step coverage of a metallization layer on an integrated circuit by use of molybdenum as an anti-reflective coating
US5622787A (en) * 1993-12-09 1997-04-22 Mitsubishi Denki Kabushiki Kaisha Mask for transferring a pattern for use in a semiconductor device and method of manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6031229A (en) * 1983-08-01 1985-02-18 Tokyo Denshi Kagaku Kabushiki Selective etching method of metal film
JPS61214524A (en) * 1985-03-18 1986-09-24 エヌ・ベー・フイリツプス・フルーイランペンフアブリケン Manufacture of semiconductor
US5066611A (en) * 1990-08-31 1991-11-19 Micron Technology, Inc. Method for improving step coverage of a metallization layer on an integrated circuit by use of molybdenum as an anti-reflective coating
US5622787A (en) * 1993-12-09 1997-04-22 Mitsubishi Denki Kabushiki Kaisha Mask for transferring a pattern for use in a semiconductor device and method of manufacturing the same
US5702849A (en) * 1993-12-09 1997-12-30 Mitsubishi Denki Kabushiki Kaisha Mask for transferring a pattern for use in a semiconductor device and method of manufacturing the same

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