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JPS5715533A - Logical array circuit possible for write-in - Google Patents

Logical array circuit possible for write-in

Info

Publication number
JPS5715533A
JPS5715533A JP9020280A JP9020280A JPS5715533A JP S5715533 A JPS5715533 A JP S5715533A JP 9020280 A JP9020280 A JP 9020280A JP 9020280 A JP9020280 A JP 9020280A JP S5715533 A JPS5715533 A JP S5715533A
Authority
JP
Japan
Prior art keywords
logical
inputted
signal lines
write
sets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9020280A
Other languages
Japanese (ja)
Other versions
JPS6335129B2 (en
Inventor
Yoshihiro Kasuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9020280A priority Critical patent/JPS5715533A/en
Publication of JPS5715533A publication Critical patent/JPS5715533A/en
Publication of JPS6335129B2 publication Critical patent/JPS6335129B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Read Only Memory (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To enable an arbitrary logical operation through electric rewriting at any time, suitable for large-scale circuit integration with good storage efficiency, by locating tri-stable storage cell in matrix and making logical operation according to the content of storage of storage cell with binary logical input signals. CONSTITUTION:A write-in controlling signal inputted from the outside through a signal line 103 is inputted to an AND logical array 2 in M rows and N columns via either one of signal lines 104-1-104-N with a write-in control circuit 1.M sets of binary logic input signals are inputted to an AND logical array 2 from the outside through signal lines 201-1-201-M, and M sets of ternary write-in input signals are inputted to the signal lines 202-1-202-M, and N sets of logical output signals in AND operation are inputted to an OR logical array 3 in L row and N column locating tri-stable storage cells in matrix via signal lines 203-1-203-N. Further, L sets of logical output signals in OR operation are outputted to signal lines 301-1-301-L from the OR logical array 3.
JP9020280A 1980-07-02 1980-07-02 Logical array circuit possible for write-in Granted JPS5715533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9020280A JPS5715533A (en) 1980-07-02 1980-07-02 Logical array circuit possible for write-in

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9020280A JPS5715533A (en) 1980-07-02 1980-07-02 Logical array circuit possible for write-in

Publications (2)

Publication Number Publication Date
JPS5715533A true JPS5715533A (en) 1982-01-26
JPS6335129B2 JPS6335129B2 (en) 1988-07-13

Family

ID=13991895

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9020280A Granted JPS5715533A (en) 1980-07-02 1980-07-02 Logical array circuit possible for write-in

Country Status (1)

Country Link
JP (1) JPS5715533A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4774421A (en) * 1984-05-03 1988-09-27 Altera Corporation Programmable logic array device using EPROM technology

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2045646A1 (en) * 1989-10-23 1991-04-24 Stuart Ashmun Pointing device with adjustable clamp attachable to a keyboard

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4774421A (en) * 1984-05-03 1988-09-27 Altera Corporation Programmable logic array device using EPROM technology

Also Published As

Publication number Publication date
JPS6335129B2 (en) 1988-07-13

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