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JPS5613584A - Setting circuit for data line potential - Google Patents

Setting circuit for data line potential

Info

Publication number
JPS5613584A
JPS5613584A JP8692779A JP8692779A JPS5613584A JP S5613584 A JPS5613584 A JP S5613584A JP 8692779 A JP8692779 A JP 8692779A JP 8692779 A JP8692779 A JP 8692779A JP S5613584 A JPS5613584 A JP S5613584A
Authority
JP
Japan
Prior art keywords
level
lines
data line
msmn
common data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8692779A
Other languages
Japanese (ja)
Other versions
JPS6256599B2 (en
Inventor
Yoshio Noguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8692779A priority Critical patent/JPS5613584A/en
Priority to US06/081,370 priority patent/US4272834A/en
Priority to DE2954688A priority patent/DE2954688C2/en
Priority to DE19792940500 priority patent/DE2940500A1/en
Publication of JPS5613584A publication Critical patent/JPS5613584A/en
Publication of JPS6256599B2 publication Critical patent/JPS6256599B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To make it possible to obtain rapidly a difference in level in the 2nd potential state by discharging the capacity of one common data line to that of the other line by way of a switching method connected between the common data lines. CONSTITUTION:Once write recovery signal phiWR1 is applied to MISMFTQ11 of switching method 9', capacitance C0 is discharged via FETQ11, so that while common data line CD0 increases in level, CD1 falls in level. Since FETQ11 is operating within the unsaturable range of output current, its operation resistance is extremely small and lines CD0 and CD1 change from the 1st potential state nearly to the 2nd potential state at a high speed. Next, when address signal Ai for address decoders 2 and 4 is switched and the memory cell is changed from MS11 over to MSmn selectively, the potentials of lines VD0 and CD1 are inverted since cross-connection points A' and B' of cell MSmn are held at the reverse potentials of lines DC0 and CD1. Consequently, level corrections by cell MSmn can be made rapidly.
JP8692779A 1978-10-06 1979-07-11 Setting circuit for data line potential Granted JPS5613584A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP8692779A JPS5613584A (en) 1979-07-11 1979-07-11 Setting circuit for data line potential
US06/081,370 US4272834A (en) 1978-10-06 1979-10-03 Data line potential setting circuit and MIS memory circuit using the same
DE2954688A DE2954688C2 (en) 1978-10-06 1979-10-05 Data line control of MISFET memory
DE19792940500 DE2940500A1 (en) 1978-10-06 1979-10-05 DATA LINE POTENTIAL ADJUSTMENT AND MIS STORAGE ARRANGEMENT WITH SUCH A CIRCUIT

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8692779A JPS5613584A (en) 1979-07-11 1979-07-11 Setting circuit for data line potential

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP63199859A Division JPH01146186A (en) 1988-08-12 1988-08-12 Mis memory circuit
JP1201172A Division JPH0756755B2 (en) 1989-08-04 1989-08-04 MIS memory circuit

Publications (2)

Publication Number Publication Date
JPS5613584A true JPS5613584A (en) 1981-02-09
JPS6256599B2 JPS6256599B2 (en) 1987-11-26

Family

ID=13900488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8692779A Granted JPS5613584A (en) 1978-10-06 1979-07-11 Setting circuit for data line potential

Country Status (1)

Country Link
JP (1) JPS5613584A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57208690A (en) * 1981-06-19 1982-12-21 Hitachi Ltd Semiconductor storage device
JPS60238267A (en) * 1984-05-07 1985-11-27 インダストリアル　メタル　プロダクツ　コ−ポレ−シヨン Precision finishing machine for surface of workpiece
JPS61139993A (en) * 1984-12-12 1986-06-27 Hitachi Micro Comput Eng Ltd Static ram
JPS6254891A (en) * 1985-09-03 1987-03-10 Sony Corp Write recovery circuit
JPS6267790A (en) * 1985-09-20 1987-03-27 Hitachi Vlsi Eng Corp Statistic type RAM
JPS62121986A (en) * 1985-11-21 1987-06-03 Sony Corp Memory circuit
JPH0278097A (en) * 1989-08-04 1990-03-19 Hitachi Ltd MIS memory circuit
JPH0729370A (en) * 1990-10-16 1995-01-31 Samsung Electron Co Ltd Data line equalizing circuit of static RAM and its equalizing method
JPH07169275A (en) * 1993-12-15 1995-07-04 Nec Corp Semiconductor memory device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3876887A (en) * 1973-07-18 1975-04-08 Intel Corp Mos amplifier
JPS52113131A (en) * 1975-09-08 1977-09-22 Toko Inc Sensing amplifier for one transistor
US4110842A (en) * 1976-11-15 1978-08-29 Advanced Micro Devices, Inc. Random access memory with memory status for improved access and cycle times
JPS5467727A (en) * 1977-10-31 1979-05-31 Ibm Ros memory circuit
JPS5485944U (en) * 1977-11-30 1979-06-18

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3876887A (en) * 1973-07-18 1975-04-08 Intel Corp Mos amplifier
JPS52113131A (en) * 1975-09-08 1977-09-22 Toko Inc Sensing amplifier for one transistor
US4110842A (en) * 1976-11-15 1978-08-29 Advanced Micro Devices, Inc. Random access memory with memory status for improved access and cycle times
JPS5467727A (en) * 1977-10-31 1979-05-31 Ibm Ros memory circuit
JPS5485944U (en) * 1977-11-30 1979-06-18

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57208690A (en) * 1981-06-19 1982-12-21 Hitachi Ltd Semiconductor storage device
JPS60238267A (en) * 1984-05-07 1985-11-27 インダストリアル　メタル　プロダクツ　コ−ポレ−シヨン Precision finishing machine for surface of workpiece
JPS61139993A (en) * 1984-12-12 1986-06-27 Hitachi Micro Comput Eng Ltd Static ram
JPS6254891A (en) * 1985-09-03 1987-03-10 Sony Corp Write recovery circuit
JPS6267790A (en) * 1985-09-20 1987-03-27 Hitachi Vlsi Eng Corp Statistic type RAM
JPS62121986A (en) * 1985-11-21 1987-06-03 Sony Corp Memory circuit
JPH0278097A (en) * 1989-08-04 1990-03-19 Hitachi Ltd MIS memory circuit
JPH0729370A (en) * 1990-10-16 1995-01-31 Samsung Electron Co Ltd Data line equalizing circuit of static RAM and its equalizing method
JPH07169275A (en) * 1993-12-15 1995-07-04 Nec Corp Semiconductor memory device

Also Published As

Publication number Publication date
JPS6256599B2 (en) 1987-11-26

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