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JPS5676612A - Zero point adjusting circuit - Google Patents

Zero point adjusting circuit

Info

Publication number
JPS5676612A
JPS5676612A JP15374979A JP15374979A JPS5676612A JP S5676612 A JPS5676612 A JP S5676612A JP 15374979 A JP15374979 A JP 15374979A JP 15374979 A JP15374979 A JP 15374979A JP S5676612 A JPS5676612 A JP S5676612A
Authority
JP
Japan
Prior art keywords
zero point
resistor
input terminal
voltage
inverting input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15374979A
Other languages
Japanese (ja)
Inventor
Fushiaki Haruhara
Hiroyuki Doi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chino Corp
Original Assignee
Chino Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chino Works Ltd filed Critical Chino Works Ltd
Priority to JP15374979A priority Critical patent/JPS5676612A/en
Publication of JPS5676612A publication Critical patent/JPS5676612A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To adjust the zero point independently of span, by supplying the zero point adjusting voltage to the inverting input terminal of an opertional amplifier via an input resistor and connecting a resistor between the inverting input terminal and ground. CONSTITUTION:An input signal voltage e1 is fed to the noninverting input terminal of an operational amplifier OP, the zero point adjusting voltage es is divided at voltage dividing resistors r1, r2 and fed to the inverting input terminal of the amplifier OP via a resistor r3. Further, between the output terminal and the inverting input terminal of the amplifier OP, a resistor r4 is connected and a resistor R is connected between this terminal and ground. With such a circuit constitution, the zero point can be adjusted independently of the span which changes the voltage es. Further, by making smaller the resistor R, the gain can easily be increased, and the effect to the output signal voltage can be made minute with the zero point adjustment to avoid the mutual interference between the span and the zero shift.
JP15374979A 1979-11-28 1979-11-28 Zero point adjusting circuit Pending JPS5676612A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15374979A JPS5676612A (en) 1979-11-28 1979-11-28 Zero point adjusting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15374979A JPS5676612A (en) 1979-11-28 1979-11-28 Zero point adjusting circuit

Publications (1)

Publication Number Publication Date
JPS5676612A true JPS5676612A (en) 1981-06-24

Family

ID=15569266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15374979A Pending JPS5676612A (en) 1979-11-28 1979-11-28 Zero point adjusting circuit

Country Status (1)

Country Link
JP (1) JPS5676612A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0478826U (en) * 1990-11-21 1992-07-09

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0478826U (en) * 1990-11-21 1992-07-09

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