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JPS5669866A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPS5669866A
JPS5669866A JP14510379A JP14510379A JPS5669866A JP S5669866 A JPS5669866 A JP S5669866A JP 14510379 A JP14510379 A JP 14510379A JP 14510379 A JP14510379 A JP 14510379A JP S5669866 A JPS5669866 A JP S5669866A
Authority
JP
Japan
Prior art keywords
layer
gate electrode
2mum
erase
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14510379A
Other languages
Japanese (ja)
Inventor
Kazuhisa Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14510379A priority Critical patent/JPS5669866A/en
Publication of JPS5669866A publication Critical patent/JPS5669866A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To obtain a nonvolatile memory enabling writing and erase by a method wherein a source layer is deepened more than a drain layer, and capacity among the layers and a gate electrode is each made unequal. CONSTITUTION:A gate electrode 13 is formed to an SiO2 film 12 on a semiconductor substrate 11, P ions are selectively injected to make up an N layer 15, As is deposited on the layer 15 and a layer 14, and the whole is thermally treated. Width xj2 and xj1 can be formed in value such as xj2 0.3mum, xj1 2mum by the difference of the speed of diffusion of P and As, channel length is shortened only by (0.3+ 2)mum to the length of the gate electrode, and gm is increased. Capacity CGS is about septuple as great as CGD because the quantitites of overlap among the gate electrode and both the source layer 15 and the drain layer 14 are each 2mum and 0.3mum. In an ROM electrically erasing, this constitution can improve the efficiency of writing and erase, shortens effective channel length, ameliorates gm and results in no trouble in a degree of integration.
JP14510379A 1979-11-09 1979-11-09 Semiconductor element Pending JPS5669866A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14510379A JPS5669866A (en) 1979-11-09 1979-11-09 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14510379A JPS5669866A (en) 1979-11-09 1979-11-09 Semiconductor element

Publications (1)

Publication Number Publication Date
JPS5669866A true JPS5669866A (en) 1981-06-11

Family

ID=15377435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14510379A Pending JPS5669866A (en) 1979-11-09 1979-11-09 Semiconductor element

Country Status (1)

Country Link
JP (1) JPS5669866A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61127179A (en) * 1984-11-21 1986-06-14 ローム・コーポレーション Electric program type memory for single transistor and method for maunfacturing and using the same
JPS62276878A (en) * 1986-05-26 1987-12-01 Hitachi Ltd Semiconductor memory
EP0307849A2 (en) * 1987-09-16 1989-03-22 National Semiconductor Corporation Application of deep-junction non-self-aligned transistors for suppressing hot carriers
JPH06140635A (en) * 1993-05-26 1994-05-20 Hitachi Ltd Manufacture of semiconductor memory device
US5407853A (en) * 1988-11-09 1995-04-18 Hitachi, Ltd. Method of making semiconductor integrated circuit device having single-element type non-volatile memory elements
US5472891A (en) * 1986-05-26 1995-12-05 Hitachi, Ltd. Method of manufacturing a semiconductor device
JP2010045374A (en) * 2009-09-09 2010-02-25 Semiconductor Energy Lab Co Ltd Semiconductor device
US10438872B2 (en) 2016-03-11 2019-10-08 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device and lead frame

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0629553A (en) * 1984-11-21 1994-02-04 Rohm Corp Memory device
JPS61127179A (en) * 1984-11-21 1986-06-14 ローム・コーポレーション Electric program type memory for single transistor and method for maunfacturing and using the same
US5656522A (en) * 1986-05-26 1997-08-12 Hitachi, Ltd. Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements
JPS62276878A (en) * 1986-05-26 1987-12-01 Hitachi Ltd Semiconductor memory
US5656839A (en) * 1986-05-26 1997-08-12 Hitachi, Ltd. Semiconductor integrated circuit device having single-element type nonvolatile memory elements
US5472891A (en) * 1986-05-26 1995-12-05 Hitachi, Ltd. Method of manufacturing a semiconductor device
EP0307849A2 (en) * 1987-09-16 1989-03-22 National Semiconductor Corporation Application of deep-junction non-self-aligned transistors for suppressing hot carriers
US5904518A (en) * 1988-11-09 1999-05-18 Hitachi, Ltd. Method of manufacturing a semiconductor IC device having single transistor type nonvolatile memory cells
US5629541A (en) * 1988-11-09 1997-05-13 Hitachi, Ltd. Semiconductor memory device constituted by single transistor type non-volatile cells and facilitated for both electrical erasing and writing of data
US5407853A (en) * 1988-11-09 1995-04-18 Hitachi, Ltd. Method of making semiconductor integrated circuit device having single-element type non-volatile memory elements
US6255690B1 (en) 1988-11-09 2001-07-03 Hitachi, Ltd. Non-volatile semiconductor memory device
US6451643B2 (en) 1988-11-09 2002-09-17 Hitachi, Ltd. Method of manufacturing a semiconductor device having non-volatile memory cell portion with single transistor type memory cells and peripheral portion with MISFETs
US6777282B2 (en) 1988-11-09 2004-08-17 Renesas Technology Corp. Method of manufacturing a semiconductor memory device having a memory cell portion including MISFETs with a floating gate and a peripheral circuit portion with MISFETs
US6960501B2 (en) 1988-11-09 2005-11-01 Renesas Technology Corp. Method of manufacturing a semiconductor memory device having a non-volatile memory cell portion with single misfet transistor type memory cells and a peripheral circuit portion with misfets
US7071050B2 (en) 1988-11-09 2006-07-04 Hitachi, Ltd. Semiconductor integrated circuit device having single-element type non-volatile memory elements
US7399667B2 (en) 1988-11-09 2008-07-15 Renesas Technology Corp. Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements
JPH06140635A (en) * 1993-05-26 1994-05-20 Hitachi Ltd Manufacture of semiconductor memory device
JP2010045374A (en) * 2009-09-09 2010-02-25 Semiconductor Energy Lab Co Ltd Semiconductor device
JP4585027B2 (en) * 2009-09-09 2010-11-24 株式会社半導体エネルギー研究所 Semiconductor device
US10438872B2 (en) 2016-03-11 2019-10-08 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device and lead frame

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