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JPS5658269A - Mos type semiconductor device - Google Patents

Mos type semiconductor device

Info

Publication number
JPS5658269A
JPS5658269A JP13382979A JP13382979A JPS5658269A JP S5658269 A JPS5658269 A JP S5658269A JP 13382979 A JP13382979 A JP 13382979A JP 13382979 A JP13382979 A JP 13382979A JP S5658269 A JPS5658269 A JP S5658269A
Authority
JP
Japan
Prior art keywords
film
type region
polycrystal
changed
conduction type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13382979A
Other languages
Japanese (ja)
Inventor
Toshiaki Ogata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP13382979A priority Critical patent/JPS5658269A/en
Publication of JPS5658269A publication Critical patent/JPS5658269A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To enable access between one conduction type region and an opposite conduction type region and increase the density of a C-MOS using the both regions by a mechanism wherein the one conduction type polycrystal Si layer is formed on the opposite conduction type Si substrate through an insulating film, and the polycrystal Si layer is annealed by laser, etc. and changed into large crystals. CONSTITUTION:An N type region is formed to a P type Si substrate 5 in a diffusion shape, a concave section is made up at a fixed region, and the whole surface containing the concave section is coated with an insulating film 6 consisting of SiO2 or Si3N4. N type impurities are contained in the whole surface and a polycrystal Si film 7 provided with conductivity is deposited, and the film 7 is left only into the concave section as the film 8 and others are removed. The remainder film 8 is annealed by laser, electron beams, etc., and the crystals are changed into large crystals, diameters thereof are several dozen mum. Thus, the P type region and the N type region are brought near through the film 6, the film 8 is changed into large crystals, and the substrate suitable for a C-MOS, etc. is manufactured.
JP13382979A 1979-10-17 1979-10-17 Mos type semiconductor device Pending JPS5658269A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13382979A JPS5658269A (en) 1979-10-17 1979-10-17 Mos type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13382979A JPS5658269A (en) 1979-10-17 1979-10-17 Mos type semiconductor device

Publications (1)

Publication Number Publication Date
JPS5658269A true JPS5658269A (en) 1981-05-21

Family

ID=15114008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13382979A Pending JPS5658269A (en) 1979-10-17 1979-10-17 Mos type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5658269A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856318A (en) * 1981-09-29 1983-04-04 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS5880831A (en) * 1981-11-10 1983-05-16 Fujitsu Ltd Manufacture of substrate for semiconductor device
JPS58114440A (en) * 1981-12-28 1983-07-07 Fujitsu Ltd Manufacture of substrate for semiconductor device
JPS58116722A (en) * 1981-12-29 1983-07-12 Fujitsu Ltd Preparation of semiconductor device
JPS58151042A (en) * 1982-03-03 1983-09-08 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS59124123A (en) * 1982-12-28 1984-07-18 Seiko Instr & Electronics Ltd Manufacture of semiconductor device
JPS6020531A (en) * 1983-06-21 1985-02-01 ソシエテ・プール・レチユード・エ・ラ・フアブリカシオン・デ・シルキユイ・アンラグレ・スペシオー―ウ―・エフ・セー・イー・エス Method of producing insulating semiconductor element on semiconductor wafer
US4879585A (en) * 1984-03-31 1989-11-07 Kabushiki Kaisha Toshiba Semiconductor device
US5517047A (en) * 1992-07-28 1996-05-14 Harris Corporation Bonded wafer processing

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856318A (en) * 1981-09-29 1983-04-04 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS5880831A (en) * 1981-11-10 1983-05-16 Fujitsu Ltd Manufacture of substrate for semiconductor device
JPH0335822B2 (en) * 1981-11-10 1991-05-29 Fujitsu Ltd
JPH0223027B2 (en) * 1981-12-28 1990-05-22 Fujitsu Ltd
JPS58114440A (en) * 1981-12-28 1983-07-07 Fujitsu Ltd Manufacture of substrate for semiconductor device
JPS58116722A (en) * 1981-12-29 1983-07-12 Fujitsu Ltd Preparation of semiconductor device
JPS58151042A (en) * 1982-03-03 1983-09-08 Fujitsu Ltd Semiconductor device and manufacture thereof
JPH0450746B2 (en) * 1982-03-03 1992-08-17 Fujitsu Ltd
JPS59124123A (en) * 1982-12-28 1984-07-18 Seiko Instr & Electronics Ltd Manufacture of semiconductor device
JPS6020531A (en) * 1983-06-21 1985-02-01 ソシエテ・プール・レチユード・エ・ラ・フアブリカシオン・デ・シルキユイ・アンラグレ・スペシオー―ウ―・エフ・セー・イー・エス Method of producing insulating semiconductor element on semiconductor wafer
US5387537A (en) * 1983-06-21 1995-02-07 Soclete Pour I'etude Et Al Fabrication De Circuits Integres Speciaux E.F.C.I.S. Process for manufacturing isolated semiconductor components in a semiconductor wafer
US5457338A (en) * 1983-06-21 1995-10-10 Societe Pour L'etude Et La Fabrication De Circuits Integres Speciaux E.F.C.I.S. Process for manufacturing isolated semi conductor components in a semi conductor wafer
US4879585A (en) * 1984-03-31 1989-11-07 Kabushiki Kaisha Toshiba Semiconductor device
US5517047A (en) * 1992-07-28 1996-05-14 Harris Corporation Bonded wafer processing
US5728624A (en) * 1992-07-28 1998-03-17 Harris Corporation Bonded wafer processing

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